Updated project sturcture

.gitignore

@@ -1,7 +1,22 @@
-/*
-!/src/
+# Ignore all, making this a whitelist
+*
+!*/
+
+# Exclude rules from ignore
 !/altera_devel.qpf
 !/altera_devel.qsf
 !/Makefile
-!/readme.md
-*.cnx
+!*.md
+!*.v
+!*.sv
+!*.py
+!sim_*.do
+!*.qip
+
+# Making sure nothing from there will be picked up
+/db
+/output_files
+/incremental_db
+/greybox_tmp
+/work
+/altera

Makefile

@@ -1,24 +1,60 @@
-QUARTUS_ROOT := /opt/intelFPGA/20.1
-QUARTUS_DIR = ${QUARTUS_ROOT}/quartus
-MODELSIM_DIR = ${QUARTUS_ROOT}/modelsim_ase
+QUARTUS_ROOT := /opt/intelFPGA/* C:/intelFPGA_lite/*
+
+### Finding quartus dir. If not found, edit QUARTUS_ROOT above
+QUARTUS_ROOT_PATH = $(word 1, $(foreach dir, $(QUARTUS_ROOT), $(wildcard $(dir))))
+ifeq ($(QUARTUS_ROOT_PATH),)
+$(error Failed to find Quartus installation dir, change QUARTUS_ROOT parameter)
+endif
+
+### Finding needed binary files
+QUARTUS_SH = $(word 1, $(wildcard $(QUARTUS_ROOT_PATH)/quartus/*/quartus_sh))
+QUARTUS_MAP = $(word 1, $(wildcard $(QUARTUS_ROOT_PATH)/quartus/*/quartus_map))
+MODELSIM_BIN = $(word 1, $(wildcard $(QUARTUS_ROOT_PATH)/modelsim_ase/*/vsim))
+
+### Checking if we have everything we need
+ifeq ($(QUARTUS_SH),)
+$(error Failed to find QUARTUS_SH)
+endif
+ifeq ($(QUARTUS_MAP),)
+$(error Failed to find QUARTUS_MAP)
+endif
+ifeq ($(MODELSIM_BIN),)
+$(error Failed to find MODELSIM_BIN)
+endif
+
+$(info QUARTUS_MAP=$(QUARTUS_MAP))
+$(info MODELSIM_BIN=$(MODELSIM_BIN))
+
+### Remaining configurations
 PROJECT_NAME = altera_devel
-MODELSIM_GUI = ${QUARTUS_DIR}/bin/quartus_sh -t "${QUARTUS_DIR}/common/tcl/internal/nativelink/qnativesim.tcl" --rtl_sim "${PROJECT_NAME}" "${PROJECT_NAME}"
-MODELSIM_BIN = ${MODELSIM_DIR}/bin/vsim
 QUARTUS_MACROS = --set VERILOG_MACRO="SYNTHESIS=1"
-VSIM_ARGS = -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L work -voptargs="+acc"
+VSIM_ARGS = -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -voptargs="+acc"
 
+
+### Optional parameters
 tb_file ?=
 tb_dir = $(dirname "${testbench_file}")
 tb_mod ?=
+do_file ?=
+
+### ================================================================
+### Commands
+### ================================================================
 
 analysis:
-	${QUARTUS_DIR}/bin/quartus_map --read_settings_files=on --write_settings_files=off ${QUARTUS_MACROS} ${PROJECT_NAME} -c ${PROJECT_NAME} --analysis_and_elaboration
+	${QUARTUS_MAP} --read_settings_files=on --write_settings_files=off ${QUARTUS_MACROS} ${PROJECT_NAME} -c ${PROJECT_NAME} --analysis_and_elaboration
 
 modelsim: analysis
-	${MODELSIM_GUI}
+	${QUARTUS_SH} -t "${QUARTUS_ROOT_PATH}/quartus/common/tcl/internal/nativelink/qnativesim.tcl" --rtl_sim "${PROJECT_NAME}" "${PROJECT_NAME}"
 
 modelsim_cli:
 	${MODELSIM_BIN} -c
 
+sim:
+	${MODELSIM_BIN} -c -do "simulation/modelsim/${do_file}"
+
+sim_gui:
+	${MODELSIM_BIN} -do "simulation/modelsim/${do_file}"
+
 testbench:
 	${MODELSIM_BIN} -c -do "vlog -sv +incdir+${tb_dir} {${tb_file}}; vsim -t 1ps ${VSIM_ARGS} ${tb_mod}; run -all"

altera_devel.qsf

@@ -42,15 +42,15 @@ set_global_assignment -name DEVICE EP4CE22F17C6
 set_global_assignment -name TOP_LEVEL_ENTITY root
 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 20.1.0
 set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:51:52  OCTOBER 03, 2020"
-set_global_assignment -name LAST_QUARTUS_VERSION "20.1.0 Lite Edition"
+set_global_assignment -name LAST_QUARTUS_VERSION "20.1.1 Lite Edition"
 set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
 set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
 set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
 set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
-set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
+set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (SystemVerilog)"
 set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
-set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
+set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "SYSTEMVERILOG HDL" -section_id eda_simulation
 set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
 set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
 set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
@@ -73,8 +73,19 @@ set_location_assignment PIN_M1 -to switches[0]
 set_location_assignment PIN_T8 -to switches[1]
 set_location_assignment PIN_B9 -to switches[2]
 set_location_assignment PIN_M15 -to switches[3]
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name SYSTEMVERILOG_FILE src/fpu32/fpu32.sv
 set_global_assignment -name SYSTEMVERILOG_FILE src/root.sv
 set_global_assignment -name QIP_FILE src/fpu32/fpu_add.qip
 set_global_assignment -name QIP_FILE src/fpu32/fpu_div.qip
+set_global_assignment -name QIP_FILE src/fpu32/fpu_mul.qip
 set_global_assignment -name QIP_FILE src/blocks/pll.qip
+set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation
+set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH root_tb -section_id eda_simulation
+set_global_assignment -name EDA_TEST_BENCH_NAME root_tb -section_id eda_simulation
+set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id root_tb
+set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME root_tb -section_id root_tb
+set_global_assignment -name EDA_TEST_BENCH_FILE src/root.sv -section_id root_tb
+set_global_assignment -name SOURCE_FILE db/altera_devel.cmp.rdb
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

readme.md

@@ -1,16 +1,33 @@
 # Altera Development Repo
 
 ### Setup
+Just run analysis
+```bash
+make analysis
+```
+if not working, specify Quartus installation directory with **QUARTUS_ROOT** parameter
+
 Start modelsim GUI
 ```bash
 make modelsim
 ```
 
-### Running benchmarks
+### Running testbench
 
-This will run test benchmark in console without opening modelsim GUI
+This will run test testbench in console without opening modelsim GUI
 ```bash
 make tb_file=${file} tb_mod=${module} testbench
 # Example
 make tb_file=./src/root.sv tb_mod=root_tb testbench
+```
+Running testbench with defined simulation tcl script.
+Scripts has be located in **simulation/modelsim/sim_\*.do**
+```bash
+# With GUI
+make do_file=${file} sim_gui
+# Without GUI
+make do_file=${file} sim
+
+# Example
+make do_file=sim_root_tb.do sim_gui
 ```

simulation/modelsim/sim_root_tb.do

@@ -0,0 +1,25 @@
+#transcript on
+if {[file exists rtl_work]} {
+	vdel -lib rtl_work -all
+}
+set rootdir [pwd]
+puts "Root Directory $rootdir"
+vlib rtl_work
+vmap work rtl_work
+
+vlog -vlog01compat -work work +incdir+${rootdir}/src/blocks ${rootdir}/src/blocks/pll.v
+vlog -vlog01compat -work work +incdir+${rootdir}/db ${rootdir}/db/pll_altpll.v
+vlog -sv -work work +incdir+${rootdir}/src ${rootdir}/src/root.sv
+vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs="+acc"  root_tb
+
+view structure
+view signals
+
+add wave -position end  sim:/root_tb/CLK50
+add wave -position end  sim:/root_tb/de0nano_0/mclk
+add wave -position end  sim:/root_tb/de0nano_0/reset
+add wave -position end  sim:/root_tb/KEYS
+add wave -position end  sim:/root_tb/LEDS
+add wave -position end  sim:/root_tb/SWITCHS
+
+run 7000

src/fpu32/fpu32.sv

@@ -0,0 +1,68 @@
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+
+module fpu32_tb();
+    reg reset, clk;
+    reg [31:0] input_a, input_b, result_add, result_div, result_mul;
+    wire nan, overflow, underflow, zero;
+
+    fpu_add adder(
+        .aclr(reset),
+        .clock(clk),
+        .input_a(input_a),
+        .input_b(input_b),
+        .result(result_add)
+    );
+
+    fpu_div divider(
+        .aclr(reset),
+        .clock(clk),
+        .input_a(input_a),
+        .input_b(input_b),
+        .result(result_div)
+    );
+
+    fpu_mul multipler(
+        .aclr(reset),
+        .clock(clk),
+        .dataa(input_a),
+        .datab(input_b),
+        .result(result_mul)
+    );
+
+    task test_inputs;
+        input [31:0] in_a, in_b, expected_add, expected_mul, expected_div;
+        input_a = in_a;
+        input_b = in_b;
+        #10ps;
+//        assert(exception_adder == 0);
+//        assert(exception_mult == 0);
+//        assert(overflow == 0);
+//        assert(underflow == 0);
+        if(result_add == expected_add)
+            $display("PASS: %H + %H = %H", input_a, input_b, expected_add);
+        else
+            $error("FAIL ADD: a=%H b=%H c=%H, expected c=%H", input_a, input_b, result_add, expected_add);
+        if(result_mul == expected_mul)
+            $display("PASS: %H * %H = %H", input_a, input_b, expected_mul);
+        else
+            $error("FAIL MUL: a=%H b=%H c=%H, expected c=%H", input_a, input_b, result_mul, expected_mul);
+        if(result_div == expected_div)
+            $display("PASS: %H * %H = %H", input_a, input_b, expected_div);
+        else
+            $error("FAIL DIV: a=%H b=%H c=%H, expected c=%H", input_a, input_b, result_div, expected_div);
+        #10ps;
+    endtask : test_inputs
+
+    initial forever #15ps clk = ~clk;
+
+    initial begin
+        clk = 0;
+        reset = 1;
+        test_inputs(32'h42480000, 32'hbf800000, 32'h42440000, 32'hc2480000, 32'hc2480000);
+
+    end
+
+
+endmodule : fpu32_tb

src/fpu32/fpu_div.v

@@ -76,8 +76,8 @@ module fpu_div (
 	altfp_div	altfp_div_component (
 				.aclr (aclr),
 				.clock (clock),
-				.dataa (dataa),
-				.datab (datab),
+				.dataa (input_a),
+				.datab (input_b),
 				.division_by_zero (sub_wire0),
 				.nan (sub_wire1),
 				.overflow (sub_wire2),

src/fpu32/fpu_mul.qip

@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "ALTFP_MULT"
+set_global_assignment -name IP_TOOL_VERSION "18.1"
+set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "fpu_mul.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "fpu_mul.cmp"]

src/root.sv

@@ -1,4 +1,9 @@
 
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+
 module root(
     input  clk,
     input  [1:0] keys,
@@ -8,12 +13,14 @@ module root(
 
     wire reset;
     wire mclk;  // Master clock for main logic
+    wire pll_lock;
 
-    assign reset = ~keys[0];
+    assign reset = ~(keys[0] & pll_lock);
     pll pll0(
-        .areset(reset),
+        .areset(~keys[0]),
         .inclk0(clk),
-        .c0(mclk)
+        .c0(mclk),
+        .locked(pll_lock)
     );
 
 endmodule : root
@@ -27,9 +34,8 @@ module root_tb ();
 
     root de0nano_0 (CLK50, KEYS, SWITCHS, LEDS);
 
-	initial forever begin
-		#10ns CLK50 = ~CLK50;
-	end
+	initial forever #10ps CLK50 = !CLK50;
+
     initial begin
         CLK50 = 0;
         KEYS = 2'b00;  // Keys are pull up, starting with both being pressed