min/ucl_project_y3

Min 49689e242c Do not simulate rst signal		il y a 6 ans
..
UCL_project_y3_run_msim_rtl_verilog.do	49689e242c Do not simulate rst signal	il y a 6 ans
modelsim.ini	de18826119 Added simulation directory	il y a 6 ans
risc8_tb_wave.do	12417f0cb5 Working processor	il y a 6 ans
risc_tb_wave.do	9d5c8e7121 Project restructure	il y a 6 ans
top_compile.do	b346abb6a3 Big project update	il y a 6 ans
top_wave.do	b346abb6a3 Big project update	il y a 6 ans
wave.do	de18826119 Added simulation directory	il y a 6 ans