Fixed all types and definitions

UCL_project_y3.qsf

@@ -77,15 +77,10 @@ set_global_assignment -name EDA_TEST_BENCH_FILE src/reg_file.sv -section_id test
 set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
 set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
 set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
-set_global_assignment -name SYSTEMVERILOG_FILE src/blocks/sign_ext.sv
-set_global_assignment -name SYSTEMVERILOG_FILE src/blocks/reg_file_tb.sv
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+set_global_assignment -name SYSTEMVERILOG_FILE src/cpu.sv
 set_global_assignment -name SYSTEMVERILOG_FILE src/blocks/reg_file.sv
 set_global_assignment -name SYSTEMVERILOG_FILE src/blocks/memory.sv
-set_global_assignment -name SYSTEMVERILOG_FILE src/blocks/instr_mem.sv
 set_global_assignment -name SYSTEMVERILOG_FILE src/blocks/alu.sv
 set_global_assignment -name SYSTEMVERILOG_FILE src/io_unit.sv
-set_global_assignment -name SYSTEMVERILOG_FILE src/general.sv
-set_global_assignment -name BDF_FILE src/cpu_block.bdf
-set_global_assignment -name SYSTEMVERILOG_FILE src/blocks/instrDecoder.sv
-set_global_assignment -name BSF_FILE src/blocks/instr_mem.bsf
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+set_global_assignment -name SYSTEMVERILOG_FILE src/general.sv

src/blocks/alu.sv

@@ -1,24 +1,12 @@
-//import project_pkg::*;
+import project_pkg::*;
 
 module alu(op, srcA, srcB, result, zero);	
-	parameter WORD=8;
 	
-	typedef enum logic [2:0] { 
-		ALU_ADD=3'b000,
-		ALU_SUB=3'b001,
-		ALU_AND=3'b010,
-		ALU_OR =3'b011,
-		ALU_SLT=3'b100,
-		ALU_NOT=3'b101,
-		ALU___0=3'b110,
-		ALU_NOP=3'b111
-	} e_alu_op;
-	
-	input  e_alu_op 			op;
-	input  logic[WORD-1:0]	srcA;
-	input  logic[WORD-1:0]	srcB;
-	output logic[WORD-1:0]	result;
-	output logic				zero;
+	input  e_alu_op 	op;
+	input  word			srcA;
+	input  word			srcB;
+	output word			result;
+	output logic		zero;
 	
 	always_comb begin
 	case(op)

src/blocks/instDecoder.bsf

@@ -1,60 +0,0 @@
-/*
-WARNING: Do NOT edit the input and output ports in this file in a text
-editor if you plan to continue editing the block that represents it in
-the Block Editor! File corruption is VERY likely to occur.
-*/
-/*
-Copyright (C) 2018  Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Intel Program License 
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors.  Please
-refer to the applicable agreement for further details.
-*/
-(header "symbol" (version "1.2"))
-(symbol
-	(rect 64 64 160 176)
-	(text "instDecoder" (rect 5 0 65 11)(font "Arial" ))
-	(text "inst" (rect 8 88 26 99)(font "Arial" ))
-	(port
-		(pt 0 48)
-		(input)
-		(text "instr" (rect 0 0 22 11)(font "Arial" ))
-		(text "instr" (rect 21 43 43 54)(font "Arial" ))
-		(line (pt 0 48)(pt 16 48)(line_width 3))
-	)
-	(port
-		(pt 96 32)
-		(output)
-		(text "opcode" (rect -88 0 -51 11)(font "Arial" ))
-		(text "opcode" (rect 48 24 85 35)(font "Arial" ))
-		(line (pt 96 32)(pt 80 32)(line_width 3))
-	)
-	(port
-		(pt 96 48)
-		(output)
-		(text "rs" (rect -88 0 -78 11)(font "Arial" ))
-		(text "rs" (rect 64 40 74 51)(font "Arial" ))
-		(line (pt 96 48)(pt 80 48)(line_width 3))
-	)
-	(port
-		(pt 96 64)
-		(output)
-		(text "rt" (rect -88 0 -80 11)(font "Arial" ))
-		(text "rt" (rect 64 56 72 67)(font "Arial" ))
-		(line (pt 96 64)(pt 80 64)(line_width 3))
-	)
-	(drawing
-		(line (pt 80 24)(pt 80 72))
-		(line (pt 80 72)(pt 16 80))
-		(line (pt 80 24)(pt 16 16))
-		(line (pt 16 16)(pt 16 80))
-	)
-)

src/blocks/instrDecoder.sv

@@ -1,14 +0,0 @@
-//import project_pkg::*;
-
-module instDecoder(instr, opcode, rs, rt);
-	input  logic [7:0]instr;
-	output logic [2:0]opcode;
-	output logic [1:0]rs;
-	output logic [1:0]rt;
-	
-	assign opcode = instr[7:4];
-	assign rs = instr[3:2];
-	assign rt = instr[1:0];
-	
-endmodule
-	

src/blocks/instr_mem.sv

@@ -2,14 +2,11 @@
 import project_pkg::*;
 
 module instr_mem(addr, instr, imm);
-	parameter WORD=8, SIZE=2**WORD;
-	typedef logic [WORD-1:0] word;
-	
 	input  word addr;
 	output word	imm;
 	output word	instr;
 	
-	logic [WORD-1:0] rom [SIZE-1:0];
+	logic [word_length-1:0] rom [rom_length-1:0];
 	
 	always_comb begin
 		rom[0] = {NOP, RegA, RegA};  // Do nothing

src/blocks/memory.sv

@@ -1,15 +1,12 @@
-//import project_pkg::*;
+import project_pkg::*;
 
-module memory(clk, addr, rd_data, wr_data, wr_en);
-	parameter WORD=8, SIZE=2**WORD;
-	
-	typedef logic [WORD-1:0] word;
+module memory(clk, addr, rd_data, wr_data, wr_en);	
 	input clk, wr_en;
 	input word addr;
 	input word wr_data;
 	output word rd_data;
 	
-	logic [WORD-1:0]memory[SIZE-1:0];
+	logic [word_size-1:0]memory[mem_size-1:0];
 	
 	always_ff@(posedge clk) begin
 		if(wr_en) memory[addr] <= wr_data;

src/blocks/reg_file.sv

@@ -1,10 +1,4 @@
 module reg_file(clk, rd_addr1, rd_addr2, rd_data1, rd_data2, wr_addr, wr_data, wr_en);
-	parameter    WORD		  = 8;
-	parameter    ADDR_SIZE = 2;
-	
-	typedef logic [WORD-1:0] word;
-	typedef logic [ADDR_SIZE-1:0] regAddr;
-	
 	input logic  clk, wr_en;
 	input regAddr 	rd_addr1;
 	input regAddr 	rd_addr2;
@@ -13,7 +7,7 @@ module reg_file(clk, rd_addr1, rd_addr2, rd_data1, rd_data2, wr_addr, wr_data, w
 	output word 	rd_data1;
 	output word 	rd_data2;
 	
-	logic        [WORD-1:0]	registry [ADDR_SIZE-1:0];
+	logic [word_size-1:0] registry [reg_size-1:0];
 	
 	always_ff@(posedge clk) begin
 		rd_data1 <= registry[rd_addr1];
@@ -22,3 +16,32 @@ module reg_file(clk, rd_addr1, rd_addr2, rd_data1, rd_data2, wr_addr, wr_data, w
 	end
 	
 endmodule
+
+module reg_file_tb;
+	logic clk, wr_en;
+	logic [1:0]rd_addr1;
+	logic [1:0]rd_addr2;
+	logic [7:0]rd_data1;
+	logic [7:0]rd_data2;
+	logic [1:0]wr_addr;
+	logic [7:0]wr_data;
+	
+	reg_file test_reg_file(clk, rd_addr1, rd_addr2, rd_data1, rd_data2, wr_addr, wr_data, wr_en);
+	
+	initial begin
+		clk = 0;
+		forever #5ns clk = ~clk;
+	end
+	
+	initial begin
+		rd_addr1 = 2'b00;
+		rd_addr2 = 2'b01;
+		wr_addr	= 2'b00;
+		wr_en 	= 0;
+		wr_data	= 8'hFF;
+		#10ns wr_en = 1;
+		#10ns wr_addr =  2'b01;
+		#10ns wr_en = 0;
+	end
+	
+endmodule

src/blocks/reg_file_tb.sv

@@ -1,28 +1 @@
-module reg_file_tb;
-	logic clk, wr_en;
-	logic [1:0]rd_addr1;
-	logic [1:0]rd_addr2;
-	logic [7:0]rd_data1;
-	logic [7:0]rd_data2;
-	logic [1:0]wr_addr;
-	logic [7:0]wr_data;
-	
-	reg_file test_reg_file(clk, rd_addr1, rd_addr2, rd_data1, rd_data2, wr_addr, wr_data, wr_en);
-	
-	initial begin
-		clk = 0;
-		forever #5ns clk = ~clk;
-	end
-	
-	initial begin
-		rd_addr1 = 2'b00;
-		rd_addr2 = 2'b01;
-		wr_addr	= 2'b00;
-		wr_en 	= 0;
-		wr_data	= 8'hFF;
-		#10ns wr_en = 1;
-		#10ns wr_addr =  2'b01;
-		#10ns wr_en = 0;
-	end
-	
-endmodule
+

src/cpu.sv

@@ -1,43 +1,8 @@
-import alu_pkg::*;
-package cpu_pkg;	
-	localparam word_length = 8;
-	localparam mem_length = 256;
-	
-	typedef enum logic [1:0] {
-		RegA = 2'b00,
-		RegB = 2'b01,
-		RegC = 2'b10,
-		RegD = 2'b11
-	} e_reg;
-	
-	typedef enum logic [3:0] { 
-		NOP =4'h0,	// No operation
-		ADD =4'h1,  // $rs = $rs + $rt
-		ADDI=4'h2,  // $rs = $rs + $imm
-		SUB =4'h3,  // $rs = $rs - $rt
-		AND =4'h4,  // $rs = $rs & $rt
-		OR  =4'h5,  // $rs = $rs | $rt
-		NOT =4'h6,  // $rs = ~$rt
-		LW  =4'h7,  // Load word from $rt to $rs
-		SW  =4'h8,  // Save word from $rt to $rs
-		WO  =4'h9,  // Write $rs to output
-		RO  =4'hA,  // Read output to $rs
-		COPY=4'hB,  // $rs = $rt
-		JEQ =4'hC,  // Jump to $imm if $rs == $rt
-		ZERO=4'hD,  // $rs = 0x00
-		__0 =4'hE,  //
-		__1 =4'hF   //
-		
-	} e_instr;
-	
-	typedef logic [word_length-1:0] word;
-	typedef logic [1:0] regAddr;
-	
-endpackage
+import project_pkg::*;
 
 module cpu(clk, rst, in_data, out_data);
 	input logic clk, rst;
-	input logic [7:0]in_data;
+	input logic  [7:0]in_data;
 	output logic [7:0]out_data;
 	
 	// ==================
@@ -46,7 +11,6 @@ module cpu(clk, rst, in_data, out_data);
 	word  pc;			// Program counter
 	word  pcn; 			// Next PC
 
-	
 	always_ff@(posedge clk, negedge rst) begin
 		if (!rst) pc <= '0;
 		else pc <= pcn;
@@ -55,9 +19,15 @@ module cpu(clk, rst, in_data, out_data);
 	// ==================
 	// Instruction memory
 	// ==================
-	e_instr instr;			// Instruction
-	word    imm;			// Immidiate value
+	word	instr, imm;
+	e_instr instr_op;
+	regAddr rs, rt;
+	
 	instr_mem #(8) IMEM(clk, pc, instr, imm);
+	// Instruction decoding
+	assign instr_op 	= instr[7:4];
+	assign rs 			= instr[3:2];
+	assign rt 			= instr[1:0];
 	
 	// =====================
 	// ALU
@@ -81,7 +51,6 @@ module cpu(clk, rst, in_data, out_data);
 	word		reg_rd_data_2;
 	reg_file #(8,2) RFILE(clk, reg_rd_addr_1, reg_rd_addr_2, reg_rd_data_1, reg_rd_data_2, reg_wr_addr, reg_wr_data, reg_wr_en);
 	
-	
 	// =====================
 	// System memory
 	// =====================
@@ -97,13 +66,13 @@ module cpu(clk, rst, in_data, out_data);
 	logic mem_to_reg;
 	
 	assign alu_srcA 	 = reg_rd_data_1;
-	assign alu_src     = (instr == ADDI);
+	assign alu_src     = (instr_op == ADDI);
 	assign alu_srcB    = (alu_src)    ? reg_rd_data_2 : imm;
 	assign reg_wr_data = (mem_to_reg) ? mem_rd_data   : alu_result;
 	
-	assign reg_wr_addr   = regAddr'(instr[5:4]);  // It's always $rs
-	assign reg_rd_addr_1 = regAddr'(instr[5:4]);  // $rs
-	assign reg_rd_addr_2 = regAddr'(instr[7:6]);  // $rt
+	assign reg_wr_addr   = rs;
+	assign reg_rd_addr_1 = rs;
+	assign reg_rd_addr_2 = rt;
 	
 	always_comb begin
 	case(instr)
@@ -123,3 +92,7 @@ module cpu(clk, rst, in_data, out_data);
 	assign pcn = (alu_zero && instr == JEQ) ? imm : pc + 1;
 	
 endmodule
+
+module cpu_tb;
+
+endmodule

src/general.sv

@@ -1,10 +1,13 @@
 package project_pkg;
 		
-	localparam word_length = 8;
-	localparam mem_length = 256;
-	
-	typedef logic [word_length-1:0] word;
-	typedef logic [1:0] regAddr;
+	localparam word_size = 8;
+	localparam mem_size = 256;
+	localparam rom_size = 256;
+	localparam reg_size = 4;
+
+	localparam reg_addr_size = $clog2(reg_size);
+	typedef logic [word_size-1:0] word;
+	typedef logic [reg_addr_size-1:0] regAddr;
 	
 	typedef enum logic [1:0] {
 		RegA = 2'b00,
@@ -33,5 +36,16 @@ package project_pkg;
 		
 	} e_instr;
 	
+		typedef enum logic [2:0] { 
+		ALU_ADD=3'b000,
+		ALU_SUB=3'b001,
+		ALU_AND=3'b010,
+		ALU_OR =3'b011,
+		ALU_SLT=3'b100,
+		ALU_NOT=3'b101,
+		ALU___0=3'b110,
+		ALU_NOP=3'b111
+	} e_alu_op;
+	
 	
 endpackage