Designing using block diagram

UCL_project_y3.qsf

@@ -38,7 +38,7 @@
 
 set_global_assignment -name FAMILY "Cyclone IV E"
 set_global_assignment -name DEVICE EP4CE22F17C6
-set_global_assignment -name TOP_LEVEL_ENTITY reg_file
+set_global_assignment -name TOP_LEVEL_ENTITY io_unit
 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.0
 set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:15:52  SEPTEMBER 19, 2019"
 set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Lite Edition"
@@ -68,19 +68,24 @@ set_location_assignment PIN_T8 -to switches[1]
 set_location_assignment PIN_B9 -to switches[2]
 set_location_assignment PIN_M15 -to switches[3]
 set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
-set_global_assignment -name SYSTEMVERILOG_FILE src/cpu.sv
-set_global_assignment -name SYSTEMVERILOG_FILE src/reg_file.sv
-set_global_assignment -name SYSTEMVERILOG_FILE src/instr_mem.sv
-set_global_assignment -name SYSTEMVERILOG_FILE src/alu.sv
-set_global_assignment -name SYSTEMVERILOG_FILE src/memory.sv
-set_global_assignment -name SYSTEMVERILOG_FILE src/io_unit.sv
-set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
-set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
-set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
 set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation
 set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH testbench_1 -section_id eda_simulation
 set_global_assignment -name EDA_TEST_BENCH_NAME testbench_1 -section_id eda_simulation
 set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id testbench_1
 set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME testbench_1 -section_id testbench_1
 set_global_assignment -name EDA_TEST_BENCH_FILE src/reg_file.sv -section_id testbench_1
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name SYSTEMVERILOG_FILE src/blocks/sign_ext.sv
+set_global_assignment -name SYSTEMVERILOG_FILE src/blocks/reg_file_tb.sv
+set_global_assignment -name SYSTEMVERILOG_FILE src/blocks/reg_file.sv
+set_global_assignment -name SYSTEMVERILOG_FILE src/blocks/memory.sv
+set_global_assignment -name SYSTEMVERILOG_FILE src/blocks/instr_mem.sv
+set_global_assignment -name SYSTEMVERILOG_FILE src/blocks/alu.sv
+set_global_assignment -name SYSTEMVERILOG_FILE src/io_unit.sv
+set_global_assignment -name SYSTEMVERILOG_FILE src/general.sv
+set_global_assignment -name BDF_FILE src/cpu_block.bdf
+set_global_assignment -name SYSTEMVERILOG_FILE src/blocks/instrDecoder.sv
+set_global_assignment -name BSF_FILE src/blocks/instr_mem.bsf
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

src/blocks/alu.bsf

@@ -0,0 +1,77 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 2018  Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Intel Program License 
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors.  Please
+refer to the applicable agreement for further details.
+*/
+(header "symbol" (version "1.2"))
+(symbol
+	(rect 64 64 216 168)
+	(text "alu" (rect 120 8 136 19)(font "Arial" ))
+	(text "inst" (rect 104 88 122 99)(font "Arial" ))
+	(port
+		(pt 0 24)
+		(input)
+		(text "src A" (rect 0 0 28 11)(font "Arial" ))
+		(text "src A" (rect 21 19 49 30)(font "Arial" ))
+		(line (pt 0 24)(pt 16 24)(line_width 3))
+	)
+	(port
+		(pt 0 80)
+		(input)
+		(text "src B" (rect 0 0 27 11)(font "Arial" ))
+		(text "src B" (rect 21 75 48 86)(font "Arial" ))
+		(line (pt 0 80)(pt 16 80)(line_width 3))
+	)
+	(port
+		(pt 56 0)
+		(input)
+		(text "op" (rect 0 0 14 11)(font "Arial" ))
+		(text "op" (rect 48 25 59 39)(font "Arial" )(vertical))
+		(line (pt 56 0)(pt 56 16)(line_width 3))
+	)
+	(port
+		(pt 152 40)
+		(output)
+		(text "zero" (rect -104 0 -81 11)(font "Arial" ))
+		(text "zero" (rect 96 32 115 43)(font "Arial" ))
+		(line (pt 152 40)(pt 136 40))
+	)
+	(port
+		(pt 152 56)
+		(output)
+		(text "result" (rect -104 0 -76 11)(font "Arial" ))
+		(text "result" (rect 96 48 124 59)(font "Arial" ))
+		(line (pt 152 56)(pt 136 56)(line_width 3))
+	)
+	(parameter
+		"WORD"
+		"8"
+		""
+		(type "PARAMETER_SIGNED_DEC")	)
+	(drawing
+		(line (pt 16 8)(pt 136 32))
+		(line (pt 136 32)(pt 136 72))
+		(line (pt 16 96)(pt 136 72))
+		(line (pt 56 48)(pt 56 56))
+		(line (pt 16 8)(pt 16 40))
+		(line (pt 16 96)(pt 16 64))
+		(line (pt 16 64)(pt 56 56))
+		(line (pt 16 40)(pt 56 48))
+	)
+	(annotation_block (parameter)(rect 272 -16 448 16))
+)

src/alu.sv

@@ -1,5 +1,8 @@
-package alu_pkg;
+//import project_pkg::*;
 
+module alu(op, srcA, srcB, result, zero);	
+	parameter WORD=8;
+	
 	typedef enum logic [2:0] { 
 		ALU_ADD=3'b000,
 		ALU_SUB=3'b001,
@@ -11,15 +14,11 @@ package alu_pkg;
 		ALU_NOP=3'b111
 	} e_alu_op;
 	
-endpackage
-
-module alu(op, srcA, srcB, result, zero);	
-	input  e_alu_op 	op;
-	input  word 		srcA;
-	input  word			srcB;
-	output word			result;
-	output logic		zero;
-	
+	input  e_alu_op 			op;
+	input  logic[WORD-1:0]	srcA;
+	input  logic[WORD-1:0]	srcB;
+	output logic[WORD-1:0]	result;
+	output logic				zero;
 	
 	always_comb begin
 	case(op)

src/blocks/instDecoder.bsf

@@ -0,0 +1,60 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 2018  Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Intel Program License 
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors.  Please
+refer to the applicable agreement for further details.
+*/
+(header "symbol" (version "1.2"))
+(symbol
+	(rect 64 64 160 176)
+	(text "instDecoder" (rect 5 0 65 11)(font "Arial" ))
+	(text "inst" (rect 8 88 26 99)(font "Arial" ))
+	(port
+		(pt 0 48)
+		(input)
+		(text "instr" (rect 0 0 22 11)(font "Arial" ))
+		(text "instr" (rect 21 43 43 54)(font "Arial" ))
+		(line (pt 0 48)(pt 16 48)(line_width 3))
+	)
+	(port
+		(pt 96 32)
+		(output)
+		(text "opcode" (rect -88 0 -51 11)(font "Arial" ))
+		(text "opcode" (rect 48 24 85 35)(font "Arial" ))
+		(line (pt 96 32)(pt 80 32)(line_width 3))
+	)
+	(port
+		(pt 96 48)
+		(output)
+		(text "rs" (rect -88 0 -78 11)(font "Arial" ))
+		(text "rs" (rect 64 40 74 51)(font "Arial" ))
+		(line (pt 96 48)(pt 80 48)(line_width 3))
+	)
+	(port
+		(pt 96 64)
+		(output)
+		(text "rt" (rect -88 0 -80 11)(font "Arial" ))
+		(text "rt" (rect 64 56 72 67)(font "Arial" ))
+		(line (pt 96 64)(pt 80 64)(line_width 3))
+	)
+	(drawing
+		(line (pt 80 24)(pt 80 72))
+		(line (pt 80 72)(pt 16 80))
+		(line (pt 80 24)(pt 16 16))
+		(line (pt 16 16)(pt 16 80))
+	)
+)

src/blocks/instrDecoder.sv

@@ -0,0 +1,14 @@
+//import project_pkg::*;
+
+module instDecoder(instr, opcode, rs, rt);
+	input  logic [7:0]instr;
+	output logic [2:0]opcode;
+	output logic [1:0]rs;
+	output logic [1:0]rt;
+	
+	assign opcode = instr[7:4];
+	assign rs = instr[3:2];
+	assign rt = instr[1:0];
+	
+endmodule
+	

src/blocks/instr_mem.bsf

@@ -0,0 +1,70 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 2018  Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Intel Program License 
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors.  Please
+refer to the applicable agreement for further details.
+*/
+(header "symbol" (version "1.2"))
+(symbol
+	(rect 64 64 184 224)
+	(text "instr_mem" (rect 5 0 58 11)(font "Arial" ))
+	(text "inst" (rect 8 144 26 155)(font "Arial" ))
+	(port
+		(pt 64 0)
+		(input)
+		(text "clk" (rect 0 0 15 11)(font "Arial" ))
+		(text "clk" (rect 56 25 67 40)(font "Arial" )(vertical))
+		(line (pt 64 0)(pt 64 17))
+	)
+	(port
+		(pt 0 56)
+		(input)
+		(text "addr" (rect 0 0 23 11)(font "Arial" ))
+		(text "addr" (rect 24 48 47 59)(font "Arial" ))
+		(line (pt 0 56)(pt 16 56)(line_width 3))
+	)
+	(port
+		(pt 120 56)
+		(output)
+		(text "instr" (rect -128 0 -106 11)(font "Arial" ))
+		(text "instr" (rect 72 48 94 59)(font "Arial" ))
+		(line (pt 120 56)(pt 104 56)(line_width 3))
+	)
+	(port
+		(pt 120 72)
+		(output)
+		(text "imm" (rect -128 0 -106 11)(font "Arial" ))
+		(text "imm" (rect 72 64 94 75)(font "Arial" ))
+		(line (pt 120 72)(pt 104 72)(line_width 3))
+	)
+	(parameter
+		"WORD"
+		"8"
+		""
+		(type "PARAMETER_SIGNED_DEC")	)
+	(parameter
+		"SIZE"
+		""
+		""
+		(type "PARAMETER_SIGNED_DEC")	)
+	(drawing
+		(line (pt 56 16)(pt 64 24))
+		(line (pt 64 24)(pt 72 16))
+		(rectangle (rect 16 16 104 136))
+	)
+	(annotation_block (parameter)(rect 264 -32 440 16))
+)

src/instr_mem.sv

@@ -1,11 +1,13 @@
-import cpu_pkg::*;
+//import cpu_pkg::*;
+import project_pkg::*;
 
-module instr_mem(clk, addr, instr, imm);
+module instr_mem(addr, instr, imm);
 	parameter WORD=8, SIZE=2**WORD;
-	input clk;
-	input  word 	addr;
-	output word		imm;
-	output e_instr instr;
+	typedef logic [WORD-1:0] word;
+	
+	input  word addr;
+	output word	imm;
+	output word	instr;
 	
 	logic [WORD-1:0] rom [SIZE-1:0];
 	
@@ -16,9 +18,9 @@ module instr_mem(clk, addr, instr, imm);
 		rom[3] = {WO, RegA, RegA};   // Show $ra
 	end
 	
-	always_ff @(posedge clk) begin
-		instr <= e_instr'(rom[addr]);
-		imm <= rom[addr + 1];
+	always_comb begin
+		instr = rom[addr];
+		imm = rom[addr + 1];
 	end
 
 endmodule

src/blocks/memory.bsf

@@ -0,0 +1,77 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 2018  Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Intel Program License 
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors.  Please
+refer to the applicable agreement for further details.
+*/
+(header "symbol" (version "1.2"))
+(symbol
+	(rect 64 64 176 248)
+	(text "memory" (rect 5 0 46 11)(font "Arial" ))
+	(text "inst" (rect 8 160 26 171)(font "Arial" ))
+	(port
+		(pt 48 0)
+		(input)
+		(text "clk" (rect 0 0 15 11)(font "Arial" ))
+		(text "clk" (rect 40 25 51 40)(font "Arial" )(vertical))
+		(line (pt 48 0)(pt 48 16))
+	)
+	(port
+		(pt 72 0)
+		(input)
+		(text "wr_en" (rect 0 0 31 11)(font "Arial" ))
+		(text "wr_en" (rect 64 25 75 56)(font "Arial" )(vertical))
+		(line (pt 72 0)(pt 72 16))
+	)
+	(port
+		(pt 0 80)
+		(input)
+		(text "addr" (rect 0 0 23 11)(font "Arial" ))
+		(text "addr" (rect 24 72 47 83)(font "Arial" ))
+		(line (pt 0 80)(pt 16 80)(line_width 3))
+	)
+	(port
+		(pt 0 112)
+		(input)
+		(text "wr_data" (rect 0 0 42 11)(font "Arial" ))
+		(text "wr_data" (rect 24 104 66 115)(font "Arial" ))
+		(line (pt 0 112)(pt 16 112)(line_width 3))
+	)
+	(port
+		(pt 112 80)
+		(output)
+		(text "rd_data" (rect -160 0 -120 11)(font "Arial" ))
+		(text "rd_data" (rect 56 72 96 83)(font "Arial" ))
+		(line (pt 112 80)(pt 96 80)(line_width 3))
+	)
+	(parameter
+		"WORD"
+		"8"
+		""
+		(type "PARAMETER_SIGNED_DEC")	)
+	(parameter
+		"SIZE"
+		""
+		""
+		(type "PARAMETER_SIGNED_DEC")	)
+	(drawing
+		(line (pt 40 16)(pt 48 24))
+		(line (pt 48 24)(pt 56 16))
+		(rectangle (rect 16 16 96 160))
+	)
+	(annotation_block (parameter)(rect 288 -32 464 16))
+)

src/memory.sv

@@ -1,11 +1,15 @@
+//import project_pkg::*;
+
 module memory(clk, addr, rd_data, wr_data, wr_en);
-	parameter WORD=8, MEM_SIZE=2**WORD;
+	parameter WORD=8, SIZE=2**WORD;
+	
+	typedef logic [WORD-1:0] word;
 	input clk, wr_en;
-	input [WORD-1:0]addr;
-	input [WORD-1:0]wr_data;
-	output logic [WORD-1:0]rd_data;
+	input word addr;
+	input word wr_data;
+	output word rd_data;
 	
-	logic [WORD-1:0]memory[MEM_SIZE-1:0];
+	logic [WORD-1:0]memory[SIZE-1:0];
 	
 	always_ff@(posedge clk) begin
 		if(wr_en) memory[addr] <= wr_data;

src/blocks/reg_file.bsf

@@ -0,0 +1,98 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 2018  Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Intel Program License 
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors.  Please
+refer to the applicable agreement for further details.
+*/
+(header "symbol" (version "1.2"))
+(symbol
+	(rect 64 64 216 240)
+	(text "reg_file" (rect 5 0 42 11)(font "Arial" ))
+	(text "inst" (rect 8 160 26 171)(font "Arial" ))
+	(port
+		(pt 72 0)
+		(input)
+		(text "clk" (rect 0 0 15 11)(font "Arial" ))
+		(text "clk" (rect 64 24 75 39)(font "Arial" )(vertical))
+		(line (pt 72 0)(pt 72 17))
+	)
+	(port
+		(pt 104 0)
+		(input)
+		(text "wr_en" (rect 0 0 31 11)(font "Arial" ))
+		(text "wr_en" (rect 96 24 107 55)(font "Arial" )(vertical))
+		(line (pt 104 0)(pt 104 17))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "rd_addr1" (rect 0 0 46 11)(font "Arial" ))
+		(text "rd_addr1" (rect 24 40 70 51)(font "Arial" ))
+		(line (pt 0 48)(pt 16 48)(line_width 3))
+	)
+	(port
+		(pt 0 64)
+		(input)
+		(text "rd_addr2" (rect 0 0 46 11)(font "Arial" ))
+		(text "rd_addr2" (rect 24 56 70 67)(font "Arial" ))
+		(line (pt 0 64)(pt 16 64)(line_width 3))
+	)
+	(port
+		(pt 0 80)
+		(input)
+		(text "wr_addr" (rect 0 0 41 11)(font "Arial" ))
+		(text "wr_addr" (rect 24 72 65 83)(font "Arial" ))
+		(line (pt 0 80)(pt 16 80)(line_width 3))
+	)
+	(port
+		(pt 0 120)
+		(input)
+		(text "wr_data" (rect 0 0 42 11)(font "Arial" ))
+		(text "wr_data" (rect 24 112 66 123)(font "Arial" ))
+		(line (pt 0 120)(pt 16 120)(line_width 3))
+	)
+	(port
+		(pt 152 96)
+		(output)
+		(text "rd_data2" (rect -152 0 -108 11)(font "Arial" ))
+		(text "rd_data2" (rect 80 88 124 99)(font "Arial" ))
+		(line (pt 152 96)(pt 136 96)(line_width 3))
+	)
+	(port
+		(pt 152 80)
+		(output)
+		(text "rd_data1" (rect -152 0 -108 11)(font "Arial" ))
+		(text "rd_data1" (rect 80 72 124 83)(font "Arial" ))
+		(line (pt 152 80)(pt 136 80)(line_width 3))
+	)
+	(parameter
+		"WORD"
+		"8"
+		""
+		(type "PARAMETER_SIGNED_DEC")	)
+	(parameter
+		"ADDR_SIZE"
+		"2"
+		""
+		(type "PARAMETER_SIGNED_DEC")	)
+	(drawing
+		(line (pt 64 16)(pt 72 24))
+		(line (pt 72 24)(pt 80 16))
+		(rectangle (rect 16 16 136 160))
+	)
+	(annotation_block (parameter)(rect 216 16 392 64))
+)

src/blocks/reg_file.sv

@@ -0,0 +1,24 @@
+module reg_file(clk, rd_addr1, rd_addr2, rd_data1, rd_data2, wr_addr, wr_data, wr_en);
+	parameter    WORD		  = 8;
+	parameter    ADDR_SIZE = 2;
+	
+	typedef logic [WORD-1:0] word;
+	typedef logic [ADDR_SIZE-1:0] regAddr;
+	
+	input logic  clk, wr_en;
+	input regAddr 	rd_addr1;
+	input regAddr 	rd_addr2;
+	input regAddr 	wr_addr;
+	input regAddr 	wr_data;
+	output word 	rd_data1;
+	output word 	rd_data2;
+	
+	logic        [WORD-1:0]	registry [ADDR_SIZE-1:0];
+	
+	always_ff@(posedge clk) begin
+		rd_data1 <= registry[rd_addr1];
+		rd_data2 <= registry[rd_addr2];
+		if(wr_en) registry[wr_addr] <= wr_data;
+	end
+	
+endmodule

src/blocks/reg_file_tb.sv

@@ -0,0 +1,28 @@
+module reg_file_tb;
+	logic clk, wr_en;
+	logic [1:0]rd_addr1;
+	logic [1:0]rd_addr2;
+	logic [7:0]rd_data1;
+	logic [7:0]rd_data2;
+	logic [1:0]wr_addr;
+	logic [7:0]wr_data;
+	
+	reg_file test_reg_file(clk, rd_addr1, rd_addr2, rd_data1, rd_data2, wr_addr, wr_data, wr_en);
+	
+	initial begin
+		clk = 0;
+		forever #5ns clk = ~clk;
+	end
+	
+	initial begin
+		rd_addr1 = 2'b00;
+		rd_addr2 = 2'b01;
+		wr_addr	= 2'b00;
+		wr_en 	= 0;
+		wr_data	= 8'hFF;
+		#10ns wr_en = 1;
+		#10ns wr_addr =  2'b01;
+		#10ns wr_en = 0;
+	end
+	
+endmodule

src/cpu.sv

@@ -1,5 +1,7 @@
 import alu_pkg::*;
 package cpu_pkg;	
+	localparam word_length = 8;
+	localparam mem_length = 256;
 	
 	typedef enum logic [1:0] {
 		RegA = 2'b00,
@@ -28,7 +30,7 @@ package cpu_pkg;
 		
 	} e_instr;
 	
-	typedef logic [7:0] word;
+	typedef logic [word_length-1:0] word;
 	typedef logic [1:0] regAddr;
 	
 endpackage
@@ -77,7 +79,7 @@ module cpu(clk, rst, in_data, out_data);
 	regAddr	reg_rd_addr_2;
 	word		reg_rd_data_1;
 	word		reg_rd_data_2;
-	reg_file #(8,4) RFILE(clk, reg_rd_addr_1, reg_rd_addr_2, reg_rd_data_1, reg_rd_data_2, reg_wr_addr, reg_wr_data, reg_wr_en);
+	reg_file #(8,2) RFILE(clk, reg_rd_addr_1, reg_rd_addr_2, reg_rd_data_1, reg_rd_data_2, reg_wr_addr, reg_wr_data, reg_wr_en);
 	
 	
 	// =====================
@@ -85,7 +87,7 @@ module cpu(clk, rst, in_data, out_data);
 	// =====================
 	logic 	mem_wr_en;
 	word		mem_rd_data;
-	memory #(8,256) RAM(clk, alu_result, mem_rd_data, reg_rd_data_2, mem_wr_en);
+	memory RAM(clk, alu_result, mem_rd_data, reg_rd_data_2, mem_wr_en);
 	
 	// =====================
 	// Control unit

src/cpu_block.bdf

@@ -0,0 +1,590 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 2018  Intel Corporation. All rights reserved.
+Your use of Intel Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Intel Program License 
+Subscription Agreement, the Intel Quartus Prime License Agreement,
+the Intel FPGA IP License Agreement, or other applicable license
+agreement, including, without limitation, that your use is for
+the sole purpose of programming logic devices manufactured by
+Intel and sold by Intel or its authorized distributors.  Please
+refer to the applicable agreement for further details.
+*/
+(header "graphic" (version "1.4"))
+(symbol
+	(rect 704 120 856 224)
+	(text "alu" (rect 120 8 136 19)(font "Arial" ))
+	(text "inst" (rect 104 88 122 99)(font "Arial" ))
+	(port
+		(pt 0 24)
+		(input)
+		(text "src A" (rect 0 0 28 11)(font "Arial" ))
+		(text "src A" (rect 21 19 49 30)(font "Arial" ))
+		(line (pt 0 24)(pt 16 24)(line_width 3))
+	)
+	(port
+		(pt 0 80)
+		(input)
+		(text "src B" (rect 0 0 27 11)(font "Arial" ))
+		(text "src B" (rect 21 75 48 86)(font "Arial" ))
+		(line (pt 0 80)(pt 16 80)(line_width 3))
+	)
+	(port
+		(pt 56 0)
+		(input)
+		(text "op" (rect 0 0 14 11)(font "Arial" ))
+		(text "op" (rect 48 25 59 39)(font "Arial" )(vertical))
+		(line (pt 56 0)(pt 56 16)(line_width 3))
+	)
+	(port
+		(pt 152 40)
+		(output)
+		(text "zero" (rect -104 0 -81 11)(font "Arial" ))
+		(text "zero" (rect 96 32 119 43)(font "Arial" ))
+		(line (pt 152 40)(pt 136 40))
+	)
+	(port
+		(pt 152 56)
+		(output)
+		(text "result" (rect -104 0 -76 11)(font "Arial" ))
+		(text "result" (rect 96 48 124 59)(font "Arial" ))
+		(line (pt 152 56)(pt 136 56)(line_width 3))
+	)
+	(parameter
+		"WORD"
+		"8"
+		""
+		(type "PARAMETER_SIGNED_DEC")	)
+	(drawing
+		(line (pt 16 8)(pt 136 32))
+		(line (pt 136 32)(pt 136 72))
+		(line (pt 16 96)(pt 136 72))
+		(line (pt 56 48)(pt 56 56))
+		(line (pt 16 8)(pt 16 40))
+		(line (pt 16 96)(pt 16 64))
+		(line (pt 16 64)(pt 56 56))
+		(line (pt 16 40)(pt 56 48))
+	)
+	(annotation_block (parameter)(rect 568 48 744 80))
+)
+(symbol
+	(rect 928 64 1040 248)
+	(text "memory" (rect 5 0 46 11)(font "Arial" ))
+	(text "inst4" (rect 8 160 32 171)(font "Arial" ))
+	(port
+		(pt 48 0)
+		(input)
+		(text "clk" (rect 0 0 15 11)(font "Arial" ))
+		(text "clk" (rect 40 25 51 40)(font "Arial" )(vertical))
+		(line (pt 48 0)(pt 48 16))
+	)
+	(port
+		(pt 72 0)
+		(input)
+		(text "wr_en" (rect 0 0 31 11)(font "Arial" ))
+		(text "wr_en" (rect 64 25 75 56)(font "Arial" )(vertical))
+		(line (pt 72 0)(pt 72 16))
+	)
+	(port
+		(pt 0 80)
+		(input)
+		(text "addr" (rect 0 0 23 11)(font "Arial" ))
+		(text "addr" (rect 24 72 47 83)(font "Arial" ))
+		(line (pt 0 80)(pt 16 80)(line_width 3))
+	)
+	(port
+		(pt 0 112)
+		(input)
+		(text "wr_data" (rect 0 0 42 11)(font "Arial" ))
+		(text "wr_data" (rect 24 104 66 115)(font "Arial" ))
+		(line (pt 0 112)(pt 16 112)(line_width 3))
+	)
+	(port
+		(pt 112 80)
+		(output)
+		(text "rd_data" (rect -160 0 -120 11)(font "Arial" ))
+		(text "rd_data" (rect 56 72 96 83)(font "Arial" ))
+		(line (pt 112 80)(pt 96 80)(line_width 3))
+	)
+	(parameter
+		"WORD"
+		"8"
+		""
+		(type "PARAMETER_SIGNED_DEC")	)
+	(parameter
+		"SIZE"
+		""
+		""
+		(type "PARAMETER_SIGNED_DEC")	)
+	(drawing
+		(line (pt 40 16)(pt 48 24))
+		(line (pt 48 24)(pt 56 16))
+		(rectangle (rect 16 16 96 160))
+	)
+	(annotation_block (parameter)(rect 704 -16 880 32))
+)
+(symbol
+	(rect -136 40 -16 200)
+	(text "instr_mem" (rect 5 0 58 11)(font "Arial" ))
+	(text "inst5" (rect 8 144 32 155)(font "Arial" ))
+	(port
+		(pt 64 0)
+		(input)
+		(text "clk" (rect 0 0 15 11)(font "Arial" ))
+		(text "clk" (rect 56 25 67 40)(font "Arial" )(vertical))
+		(line (pt 64 0)(pt 64 17))
+	)
+	(port
+		(pt 0 56)
+		(input)
+		(text "addr" (rect 0 0 23 11)(font "Arial" ))
+		(text "addr" (rect 24 48 47 59)(font "Arial" ))
+		(line (pt 0 56)(pt 16 56)(line_width 3))
+	)
+	(port
+		(pt 120 56)
+		(output)
+		(text "instr" (rect -128 0 -106 11)(font "Arial" ))
+		(text "instr" (rect 72 48 94 59)(font "Arial" ))
+		(line (pt 120 56)(pt 104 56)(line_width 3))
+	)
+	(port
+		(pt 120 72)
+		(output)
+		(text "imm" (rect -128 0 -106 11)(font "Arial" ))
+		(text "imm" (rect 72 64 94 75)(font "Arial" ))
+		(line (pt 120 72)(pt 104 72)(line_width 3))
+	)
+	(parameter
+		"WORD"
+		"8"
+		""
+		(type "PARAMETER_SIGNED_DEC")	)
+	(parameter
+		"SIZE"
+		""
+		""
+		(type "PARAMETER_SIGNED_DEC")	)
+	(drawing
+		(line (pt 56 16)(pt 64 24))
+		(line (pt 64 24)(pt 72 16))
+		(rectangle (rect 16 16 104 136))
+	)
+	(annotation_block (parameter)(rect -48 -32 128 16))
+)
+(symbol
+	(rect 192 64 344 240)
+	(text "reg_file" (rect 5 0 42 11)(font "Arial" ))
+	(text "inst6" (rect 8 160 32 171)(font "Arial" ))
+	(port
+		(pt 72 0)
+		(input)
+		(text "clk" (rect 0 0 15 11)(font "Arial" ))
+		(text "clk" (rect 64 24 75 39)(font "Arial" )(vertical))
+		(line (pt 72 0)(pt 72 17))
+	)
+	(port
+		(pt 104 0)
+		(input)
+		(text "wr_en" (rect 0 0 31 11)(font "Arial" ))
+		(text "wr_en" (rect 96 24 107 55)(font "Arial" )(vertical))
+		(line (pt 104 0)(pt 104 17))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "rd_addr1" (rect 0 0 46 11)(font "Arial" ))
+		(text "rd_addr1" (rect 24 40 70 51)(font "Arial" ))
+		(line (pt 0 48)(pt 16 48)(line_width 3))
+	)
+	(port
+		(pt 0 64)
+		(input)
+		(text "rd_addr2" (rect 0 0 46 11)(font "Arial" ))
+		(text "rd_addr2" (rect 24 56 70 67)(font "Arial" ))
+		(line (pt 0 64)(pt 16 64)(line_width 3))
+	)
+	(port
+		(pt 0 80)
+		(input)
+		(text "wr_addr" (rect 0 0 41 11)(font "Arial" ))
+		(text "wr_addr" (rect 24 72 65 83)(font "Arial" ))
+		(line (pt 0 80)(pt 16 80)(line_width 3))
+	)
+	(port
+		(pt 0 120)
+		(input)
+		(text "wr_data" (rect 0 0 42 11)(font "Arial" ))
+		(text "wr_data" (rect 24 112 66 123)(font "Arial" ))
+		(line (pt 0 120)(pt 16 120)(line_width 3))
+	)
+	(port
+		(pt 152 96)
+		(output)
+		(text "rd_data2" (rect -152 0 -108 11)(font "Arial" ))
+		(text "rd_data2" (rect 80 88 124 99)(font "Arial" ))
+		(line (pt 152 96)(pt 136 96)(line_width 3))
+	)
+	(port
+		(pt 152 80)
+		(output)
+		(text "rd_data1" (rect -152 0 -108 11)(font "Arial" ))
+		(text "rd_data1" (rect 80 72 124 83)(font "Arial" ))
+		(line (pt 152 80)(pt 136 80)(line_width 3))
+	)
+	(parameter
+		"WORD"
+		"8"
+		""
+		(type "PARAMETER_SIGNED_DEC")	)
+	(parameter
+		"ADDR_SIZE"
+		"2"
+		""
+		(type "PARAMETER_SIGNED_DEC")	)
+	(drawing
+		(line (pt 64 16)(pt 72 24))
+		(line (pt 72 24)(pt 80 16))
+		(rectangle (rect 16 16 136 160))
+	)
+	(annotation_block (parameter)(rect 312 0 488 48))
+)
+(symbol
+	(rect 16 48 112 160)
+	(text "instDecoder" (rect 5 0 65 11)(font "Arial" ))
+	(text "inst1" (rect 8 88 32 99)(font "Arial" ))
+	(port
+		(pt 0 48)
+		(input)
+		(text "instr" (rect 0 0 22 11)(font "Arial" ))
+		(text "instr" (rect 21 43 43 54)(font "Arial" ))
+		(line (pt 0 48)(pt 16 48)(line_width 3))
+	)
+	(port
+		(pt 96 32)
+		(output)
+		(text "opcode" (rect -88 0 -51 11)(font "Arial" ))
+		(text "opcode" (rect 48 24 85 35)(font "Arial" ))
+		(line (pt 96 32)(pt 80 32)(line_width 3))
+	)
+	(port
+		(pt 96 48)
+		(output)
+		(text "rs" (rect -88 0 -78 11)(font "Arial" ))
+		(text "rs" (rect 64 40 74 51)(font "Arial" ))
+		(line (pt 96 48)(pt 80 48)(line_width 3))
+	)
+	(port
+		(pt 96 64)
+		(output)
+		(text "rt" (rect -88 0 -80 11)(font "Arial" ))
+		(text "rt" (rect 64 56 72 67)(font "Arial" ))
+		(line (pt 96 64)(pt 80 64)(line_width 3))
+	)
+	(drawing
+		(line (pt 80 24)(pt 80 72))
+		(line (pt 80 72)(pt 16 80))
+		(line (pt 80 24)(pt 16 16))
+		(line (pt 16 16)(pt 16 80))
+	)
+)
+(symbol
+	(rect 512 160 624 248)
+	(text "BUSMUX" (rect 28 72 96 88)(font "Arial" (font_size 10)))
+	(text "srcB_sel" (rect 3 -2 45 11)(font "Intel Clear" ))
+	(port
+		(pt 0 24)
+		(input)
+		(text "datab[WIDTH-1..0]" (rect 6 51 112 64)(font "Arial" (font_size 8)))
+		(text "datab[]" (rect 6 24 46 37)(font "Arial" (font_size 8)))
+		(line (pt 0 24)(pt 44 24)(line_width 3))
+	)
+	(port
+		(pt 56 0)
+		(input)
+		(text "sel" (rect 59 70 76 83)(font "Arial" (font_size 8)))
+		(text "sel" (rect 59 5 76 18)(font "Arial" (font_size 8)))
+		(line (pt 56 0)(pt 56 16))
+	)
+	(port
+		(pt 0 56)
+		(input)
+		(text "dataa[WIDTH-1..0]" (rect 6 19 112 32)(font "Arial" (font_size 8)))
+		(text "dataa[]" (rect 6 56 46 69)(font "Arial" (font_size 8)))
+		(line (pt 0 56)(pt 44 56)(line_width 3))
+	)
+	(port
+		(pt 112 40)
+		(output)
+		(text "result[WIDTH-1..0]" (rect 75 35 181 48)(font "Arial" (font_size 8)))
+		(text "result[]" (rect 75 40 113 53)(font "Arial" (font_size 8)))
+		(line (pt 68 40)(pt 112 40)(line_width 3))
+	)
+	(parameter
+		"WIDTH"
+		"8"
+		"Width of I/O, any integer > 0"
+		" 1" " 2" " 3" " 4" " 5" " 6" " 7" " 8" " 9" "10" "11" "12" "13" "14" "15" "16" "20" "24" "28" "32" "40" "48" "56" "64" 
+	)
+	(drawing
+		(text "0" (rect 52 47 60 57)(font "Arial" (font_size 6)))
+		(text "1" (rect 52 23 60 33)(font "Arial" (font_size 6)))
+		(line (pt 68 24)(pt 68 56))
+		(line (pt 44 8)(pt 44 72))
+		(line (pt 44 72)(pt 68 56))
+		(line (pt 44 8)(pt 68 24))
+	)
+	(flipx)
+	(annotation_block (parameter)(rect 592 88 714 118))
+)
+(symbol
+	(rect 1128 88 1240 176)
+	(text "BUSMUX" (rect 28 72 96 88)(font "Arial" (font_size 10)))
+	(text "mem_to_reg" (rect 3 -2 67 11)(font "Intel Clear" ))
+	(port
+		(pt 0 24)
+		(input)
+		(text "datab[WIDTH-1..0]" (rect 6 51 112 64)(font "Arial" (font_size 8)))
+		(text "datab[]" (rect 6 24 46 37)(font "Arial" (font_size 8)))
+		(line (pt 0 24)(pt 44 24)(line_width 3))
+	)
+	(port
+		(pt 56 0)
+		(input)
+		(text "sel" (rect 59 70 76 83)(font "Arial" (font_size 8)))
+		(text "sel" (rect 59 5 76 18)(font "Arial" (font_size 8)))
+		(line (pt 56 0)(pt 56 16))
+	)
+	(port
+		(pt 0 56)
+		(input)
+		(text "dataa[WIDTH-1..0]" (rect 6 19 112 32)(font "Arial" (font_size 8)))
+		(text "dataa[]" (rect 6 56 46 69)(font "Arial" (font_size 8)))
+		(line (pt 0 56)(pt 44 56)(line_width 3))
+	)
+	(port
+		(pt 112 40)
+		(output)
+		(text "result[WIDTH-1..0]" (rect 75 35 181 48)(font "Arial" (font_size 8)))
+		(text "result[]" (rect 75 40 113 53)(font "Arial" (font_size 8)))
+		(line (pt 68 40)(pt 112 40)(line_width 3))
+	)
+	(parameter
+		"WIDTH"
+		"8"
+		"Width of I/O, any integer > 0"
+		" 1" " 2" " 3" " 4" " 5" " 6" " 7" " 8" " 9" "10" "11" "12" "13" "14" "15" "16" "20" "24" "28" "32" "40" "48" "56" "64" 
+	)
+	(drawing
+		(text "0" (rect 52 47 60 57)(font "Arial" (font_size 6)))
+		(text "1" (rect 52 23 60 33)(font "Arial" (font_size 6)))
+		(line (pt 68 24)(pt 68 56))
+		(line (pt 44 8)(pt 44 72))
+		(line (pt 44 72)(pt 68 56))
+		(line (pt 44 8)(pt 68 24))
+	)
+	(flipx)
+	(annotation_block (parameter)(rect 1240 56 1362 86))
+)
+(connector
+	(pt 264 -64)
+	(pt 264 64)
+)
+(connector
+	(pt -72 -64)
+	(pt -72 40)
+)
+(connector
+	(pt -16 96)
+	(pt 16 96)
+	(bus)
+)
+(connector
+	(pt 112 96)
+	(pt 160 96)
+	(bus)
+)
+(connector
+	(pt 192 112)
+	(pt 160 112)
+	(bus)
+)
+(connector
+	(pt 192 144)
+	(pt 160 144)
+	(bus)
+)
+(connector
+	(pt 160 96)
+	(pt 160 112)
+	(bus)
+)
+(connector
+	(pt 160 112)
+	(pt 160 144)
+	(bus)
+)
+(connector
+	(pt 112 112)
+	(pt 136 112)
+	(bus)
+)
+(connector
+	(pt 136 112)
+	(pt 136 128)
+	(bus)
+)
+(connector
+	(pt 192 128)
+	(pt 136 128)
+	(bus)
+)
+(connector
+	(pt 976 -64)
+	(pt 976 64)
+)
+(connector
+	(pt 928 144)
+	(pt 896 144)
+	(bus)
+)
+(connector
+	(pt -72 -64)
+	(pt 264 -64)
+)
+(connector
+	(pt 264 -64)
+	(pt 976 -64)
+)
+(connector
+	(pt 896 176)
+	(pt 856 176)
+	(bus)
+)
+(connector
+	(pt 344 144)
+	(pt 704 144)
+	(bus)
+)
+(connector
+	(pt 624 200)
+	(pt 704 200)
+	(bus)
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+(connector
+	(pt 1040 144)
+	(pt 1128 144)
+	(bus)
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+	(pt 1128 112)
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+	(bus)
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+	(pt 1072 112)
+	(pt 1072 48)
+	(bus)
+)
+(connector
+	(pt 1072 48)
+	(pt 896 48)
+	(bus)
+)
+(connector
+	(pt 896 48)
+	(pt 896 144)
+	(bus)
+)
+(connector
+	(pt 896 144)
+	(pt 896 176)
+	(bus)
+)
+(connector
+	(pt 1240 128)
+	(pt 1256 128)
+	(bus)
+)
+(connector
+	(pt 1256 128)
+	(pt 1256 360)
+	(bus)
+)
+(connector
+	(pt 1256 360)
+	(pt 160 360)
+	(bus)
+)
+(connector
+	(pt 192 184)
+	(pt 160 184)
+	(bus)
+)
+(connector
+	(pt 160 184)
+	(pt 160 360)
+	(bus)
+)
+(connector
+	(pt -16 112)
+	(pt 0 112)
+	(bus)
+)
+(connector
+	(pt 0 264)
+	(pt 0 112)
+	(bus)
+)
+(connector
+	(pt 0 264)
+	(pt 8 264)
+	(bus)
+)
+(connector
+	(pt 928 176)
+	(pt 912 176)
+	(bus)
+)
+(connector
+	(pt 912 176)
+	(pt 912 256)
+	(bus)
+)
+(connector
+	(pt 912 256)
+	(pt 480 256)
+	(bus)
+)
+(connector
+	(pt 480 184)
+	(pt 512 184)
+	(bus)
+)
+(connector
+	(pt 344 160)
+	(pt 480 160)
+	(bus)
+)
+(connector
+	(pt 480 160)
+	(pt 480 184)
+	(bus)
+)
+(connector
+	(pt 480 184)
+	(pt 480 256)
+	(bus)
+)
+(junction (pt 264 -64))
+(junction (pt 160 112))
+(junction (pt 896 144))
+(junction (pt 480 184))

src/general.sv

@@ -0,0 +1,37 @@
+package project_pkg;
+		
+	localparam word_length = 8;
+	localparam mem_length = 256;
+	
+	typedef logic [word_length-1:0] word;
+	typedef logic [1:0] regAddr;
+	
+	typedef enum logic [1:0] {
+		RegA = 2'b00,
+		RegB = 2'b01,
+		RegC = 2'b10,
+		RegD = 2'b11
+	} e_reg;
+	
+	typedef enum logic [3:0] { 
+		NOP =4'h0,	// No operation
+		ADD =4'h1,  // $rs = $rs + $rt
+		ADDI=4'h2,  // $rs = $rs + $imm
+		SUB =4'h3,  // $rs = $rs - $rt
+		AND =4'h4,  // $rs = $rs & $rt
+		OR  =4'h5,  // $rs = $rs | $rt
+		NOT =4'h6,  // $rs = ~$rt
+		LW  =4'h7,  // Load word from $rt to $rs
+		SW  =4'h8,  // Save word from $rt to $rs
+		WO  =4'h9,  // Write $rs to output
+		RO  =4'hA,  // Read output to $rs
+		COPY=4'hB,  // $rs = $rt
+		JEQ =4'hC,  // Jump to $imm if $rs == $rt
+		ZERO=4'hD,  // $rs = 0x00
+		__0 =4'hE,  //
+		__1 =4'hF   //
+		
+	} e_instr;
+	
+	
+endpackage

src/instruction_mem.sv

@@ -1,21 +0,0 @@
-module instruction_mem(addr, data);
-parameter WORD=8;
-input [WORD-1:0] addr;
-output logic [WORD-1:0] data;
-
-always_comb begin
-	case(addr)
-		0: data <= 8'b1000_0000;
-		1: data <= 8'b0100_0000;
-		2: data <= 8'b0010_0000;
-		3: data <= 8'b0001_0000;
-		4: data <= 8'b0000_1000;
-		5: data <= 8'b0000_0100;
-		6: data <= 8'b0000_0010;
-		7: data <= 8'b0000_0001;
-	-	8: data <= 8'hFF;
-		default: data = 0;
-	endcase
-end
- 
-endmodule

src/io_unit.sv

@@ -6,6 +6,6 @@ module io_unit(switches, keys, leds);
 	
 	assign rst = keys[0];
 	assign clk = keys[1];
-	cpu CPU(clk, rst);
+//	cpu CPU(clk, rst);
 	
 endmodule

src/reg_file.sv

@@ -1,52 +0,0 @@
-module reg_file(clk, rd_addr1, rd_addr2, rd_data1, rd_data2, wr_addr, wr_data, wr_en);
-	parameter    WORD		  = 8;
-	parameter    REG_SIZE  = 4;
-	localparam   ADDR_SIZE = $clog2(REG_SIZE);
-	
-	input logic  clk, wr_en;
-	input 		 [ADDR_SIZE-1:0] rd_addr1;
-	input 		 [ADDR_SIZE-1:0] rd_addr2;
-	input 		 [ADDR_SIZE-1:0] wr_addr;
-	input 		 [WORD-1:0]		  wr_data;
-	output logic [WORD-1:0]      rd_data1;
-	output logic [WORD-1:0]      rd_data2;
-	
-	logic        [WORD-1:0]	registry [ADDR_SIZE-1:0];
-	
-	always_ff@(posedge clk) begin
-		rd_data1 <= registry[rd_addr1];
-		rd_data2 <= registry[rd_addr2];
-		if(wr_en) registry[wr_addr] <= wr_data;
-	end
-	
-endmodule
-
-
-module reg_file_tb;
-	logic clk, wr_en;
-	logic [1:0]rd_addr1;
-	logic [1:0]rd_addr2;
-	logic [7:0]rd_data1;
-	logic [7:0]rd_data2;
-	logic [1:0]wr_addr;
-	logic [7:0]wr_data;
-	
-	reg_file test_reg_file(clk, rd_addr1, rd_addr2, rd_data1, rd_data2, wr_addr, wr_data, wr_en);
-	
-	initial begin
-		clk = 0;
-		forever #5ns clk = ~clk;
-	end
-	
-	initial begin
-		rd_addr1 = 2'b00;
-		rd_addr2 = 2'b01;
-		wr_addr	= 2'b00;
-		wr_en 	= 0;
-		wr_data	= 8'hFF;
-		#10ns wr_en = 1;
-		#5ns wr_en = 0;
-	end
-	
-endmodule
-