min/ucl_project_y3 @ f0c5ea9355de8f569ea6ad72f5ca24b0e91116b5

Min 49689e242c Do not simulate rst signal		6 年之前
..
UCL_project_y3_run_msim_rtl_verilog.do	49689e242c Do not simulate rst signal	6 年之前
modelsim.ini	de18826119 Added simulation directory	6 年之前
risc8_tb_wave.do	12417f0cb5 Working processor	6 年之前
risc_tb_wave.do	9d5c8e7121 Project restructure	6 年之前
top_compile.do	b346abb6a3 Big project update	6 年之前
top_wave.do	b346abb6a3 Big project update	6 年之前
wave.do	de18826119 Added simulation directory	6 年之前