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ucl_project_y3
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ucl_project_y3
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simulation
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modelsim
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top_wave.do

top_wave.do 4.5 KB
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  1. onerror {resume}
    2. 

  2. quietly WaveActivateNextPane {} 0
    3. 

  3. add wave -noupdate /top_tb/CLK50
    4. 

  4. add wave -noupdate -label MCLK /top_tb/top0/cpu_block0/dpath0/clk
    5. 

  5. add wave -noupdate -label RESET /top_tb/top0/cpu_block0/dpath0/rst
    6. 

  6. add wave -noupdate -label PC_FF -radix hexadecimal /top_tb/top0/cpu_block0/rom_block0/ff_addr
    7. 

  7. add wave -noupdate -group PC -label PC -radix hexadecimal /top_tb/top0/cpu_block0/dpath0/pc
    8. 

  8. add wave -noupdate -group PC -label PCX -radix hexadecimal -radixshowbase 0 /top_tb/top0/cpu_block0/dpath0/pcx
    9. 

  9. add wave -noupdate -group PC -label PC_OFF -radix unsigned -radixshowbase 0 /top_tb/top0/cpu_block0/dpath0/pc_off
    10. 

  10. add wave -noupdate -group PC /top_tb/top0/cpu_block0/cdi0/pcop
    11. 

  11. add wave -noupdate -label operation /top_tb/top0/cpu_block0/ctrl0/op
    12. 

  12. add wave -noupdate -color {Cadet Blue} -label REG_FILE -radix hexadecimal /top_tb/top0/cpu_block0/dpath0/reg0/registry
    13. 

  13. add wave -noupdate -expand -group ALU -label ALU_OP /top_tb/top0/cpu_block0/cdi0/alu_op
    14. 

  14. add wave -noupdate -expand -group ALU -label SRC_A -radix hexadecimal /top_tb/top0/cpu_block0/dpath0/srcA
    15. 

  15. add wave -noupdate -expand -group ALU -label SRC_B -radix hexadecimal /top_tb/top0/cpu_block0/dpath0/srcB
    16. 

  16. add wave -noupdate -expand -group ALU -label ALU_EQ /top_tb/top0/cpu_block0/dpath0/alu_eq
    17. 

  17. add wave -noupdate -expand -group ALU -label ALU_GT /top_tb/top0/cpu_block0/dpath0/alu_gt
    18. 

  18. add wave -noupdate -expand -group ALU -label ALU_ZERO /top_tb/top0/cpu_block0/dpath0/alu_zero
    19. 

  19. add wave -noupdate -expand -group ALU -label ALU_R_Lo -radix hexadecimal /top_tb/top0/cpu_block0/dpath0/alu_rlo
    20. 

  20. add wave -noupdate -expand -group ALU -label ALU_R_Hi -radix hexadecimal /top_tb/top0/cpu_block0/dpath0/alu_rhi
    21. 

  21. add wave -noupdate -expand -group COMS -label COM_ADDR -radix hexadecimal /top_tb/top0/port0/com_addr
    22. 

  22. add wave -noupdate -expand -group COMS -label COM_WR -radix hexadecimal /top_tb/top0/port0/com_wr
    23. 

  23. add wave -noupdate -expand -group COMS -label COM_RD -radix hexadecimal -childformat {{{/top_tb/top0/port0/com_rd[7]} -radix hexadecimal} {{/top_tb/top0/port0/com_rd[6]} -radix hexadecimal} {{/top_tb/top0/port0/com_rd[5]} -radix hexadecimal} {{/top_tb/top0/port0/com_rd[4]} -radix hexadecimal} {{/top_tb/top0/port0/com_rd[3]} -radix hexadecimal} {{/top_tb/top0/port0/com_rd[2]} -radix hexadecimal} {{/top_tb/top0/port0/com_rd[1]} -radix hexadecimal} {{/top_tb/top0/port0/com_rd[0]} -radix hexadecimal}} -subitemconfig {{/top_tb/top0/port0/com_rd[7]} {-height 17 -radix hexadecimal} {/top_tb/top0/port0/com_rd[6]} {-height 17 -radix hexadecimal} {/top_tb/top0/port0/com_rd[5]} {-height 17 -radix hexadecimal} {/top_tb/top0/port0/com_rd[4]} {-height 17 -radix hexadecimal} {/top_tb/top0/port0/com_rd[3]} {-height 17 -radix hexadecimal} {/top_tb/top0/port0/com_rd[2]} {-height 17 -radix hexadecimal} {/top_tb/top0/port0/com_rd[1]} {-height 17 -radix hexadecimal} {/top_tb/top0/port0/com_rd[0]} {-height 17 -radix hexadecimal}} /top_tb/top0/port0/com_rd
    24. 

  24. add wave -noupdate -expand -group COMS /top_tb/SWITCH
    25. 

  25. add wave -noupdate -expand -group COMS /top_tb/LED
    26. 

  26. add wave -noupdate -expand -group MEMORY -color Sienna -label RAM_ADDR -radix hexadecimal /top_tb/top0/port0/ram_addr
    27. 

  27. add wave -noupdate -expand -group MEMORY -color Sienna -label RAM_WR -radix hexadecimal /top_tb/top0/port0/ram_wr_data
    28. 

  28. add wave -noupdate -expand -group MEMORY -color Sienna -label RAM_RD -radix hexadecimal /top_tb/top0/port0/ram_rd_data
    29. 

  29. add wave -noupdate -expand -group MEMORY -color Sienna -label RAM_WRE /top_tb/top0/port0/ram_wr_en
    30. 

  30. add wave -noupdate -expand -group MEMORY -color Sienna -label RAM_RDE /top_tb/top0/port0/ram_rd_en
    31. 

  31. add wave -noupdate -expand -group MEMORY -label state /top_tb/top0/sdram0/state
    32. 

  32. add wave -noupdate -expand -group MEMORY -label rd_ready /top_tb/top0/sdram0/sdram_control0/rd_ready
    33. 

  33. add wave -noupdate -expand -group MEMORY -label busy /top_tb/top0/sdram0/sdram_control0/busy
    34. 

  34. add wave -noupdate -expand -group MEMORY -label wr_en /top_tb/top0/sdram0/sdram_control0/wr_enable
    35. 

  35. add wave -noupdate -expand -group MEMORY -label rd_en /top_tb/top0/sdram0/sdram_control0/rd_enable
    36. 

  36. TreeUpdate [SetDefaultTree]
    37. 

  37. WaveRestoreCursors {{Cursor 1} {3529488 ps} 0}
    38. 

  38. quietly wave cursor active 1
    39. 

  39. configure wave -namecolwidth 150
    40. 

  40. configure wave -valuecolwidth 100
    41. 

  41. configure wave -justifyvalue left
    42. 

  42. configure wave -signalnamewidth 0
    43. 

  43. configure wave -snapdistance 10
    44. 

  44. configure wave -datasetprefix 0
    45. 

  45. configure wave -rowmargin 4
    46. 

  46. configure wave -childrowmargin 2
    47. 

  47. configure wave -gridoffset 0
    48. 

  48. configure wave -gridperiod 1
    49. 

  49. configure wave -griddelta 40
    50. 

  50. configure wave -timeline 0
    51. 

  51. configure wave -timelineunits ps
    52. 

  52. update
    53. 

  53. WaveRestoreZoom {0 ps} {10361984 ps}
    54.