min/ucl_project_y3 @ 3489b237d542b7ff770dc31cf42b8e6d0ca1f2ea

Min 12417f0cb5 Working processor		6 лет назад
..
UCL_project_y3_run_msim_rtl_verilog.do	aa42f5562f Project update	6 лет назад
modelsim.ini	de18826119 Added simulation directory	6 лет назад
risc8_tb_wave.do	12417f0cb5 Working processor	6 лет назад
risc_tb_wave.do	9d5c8e7121 Project restructure	6 лет назад
wave.do	de18826119 Added simulation directory	6 лет назад