Commit History

Author SHA1 Message Date
  Min aa42f5562f Project update 6 years ago
  Min 444de8d425 Improved RAM simulaiton 6 years ago
  Min f8e4f077c7 Fixed compiling on instruction ROM 6 years ago
  Min ff13c35437 Added makefile assembly compiler 6 years ago
  Min b69c617c7e Updated ROM 6 years ago
  Min 582d751eae Implemented working control 6 years ago
  Min 5cfd8f917f Added modelsim to makefile 6 years ago
  Min 8bec823f2c Added makefile 6 years ago
  Min a7515eb5dd Control Block Updates 6 years ago
  Min 76da17477b Updated readme 6 years ago
  Min 2f2367f684 Restructrure 6 years ago
  Min 9d5c8e7121 Project restructure 6 years ago
  Min 04e6bdfb83 Improved ALU 6 years ago
  Min b2ea53b31b Updated readme 6 years ago
  Min 5cd9c4d626 Cleanup 6 years ago
  Min f70be03094 Cleanup 6 years ago
  Min 765071d73f Testiug UART 6 years ago
  Min 67bb6d0dec Added docs 6 years ago
  Min de18826119 Added simulation directory 6 years ago
  Min c49e82bd6d Added BS compiler 6 years ago
  Min 6260264fc6 Added readme & docs 6 years ago
  Min 067445f9da Implemented PUSH/POP instructions 6 years ago
  Min 31ee682781 Implemented alu extened instructions 6 years ago
  Min 6e042dd306 Updated gitignore 6 years ago
  Min 54527fde08 Implemented jump instr 6 years ago
  Min e0bbee7352 Assemby compiler 6 years ago
  Min 78d8f8dc05 Working prototyte 6 years ago
  Min 880b1f42e9 Working prototype 6 years ago
  Min 02b79c42f5 separate cpu modules WIP 6 years ago
  Min 68c3a4e498 cleanup 6 years ago