Added makefile assembly compiler

Makefile

@@ -6,15 +6,19 @@ QUARTUS_MAP = ${QUARTUS_DIR}/bin/quartus_map --read_settings_files=on --write_se
 MODELSIM_GUI = ${QUARTUS_DIR}/bin/quartus_sh -t "${QUARTUS_DIR}/common/tcl/internal/nativelink/qnativesim.tcl" --rtl_sim "${PROJECT_NAME}" "${PROJECT_NAME}"
 MODELSIM_BIN = ${MODELSIM_DIR}/bin/vsim
 
+GENTABLE_BIN = python3 tools/gen_sv.py
+ASMC = python3 tools/asm_compiler.py
+
+MEMDEP = memory/risc8_test.asm
+MEMRES = $(MEMDEP:.asm=.mem)
 
 # Genreate sv case table from csv
-GENSV = python3 tools/gen_sv.py
 GENTABLE_CSV = src/risc/controller.csv
 define execute-gentable
-$(GENSV) $(1) $(1:.csv=.sv)
+$(GENTABLE_BIN) $(1) $(1:.csv=.sv)
 endef
 
-analysis:
+analysis: compile_mem
 	${QUARTUS_MAP} --analysis_and_elaboration
 
 synthesis:
@@ -29,6 +33,15 @@ modelsim_gui:
 compile:
 	${MODELSIM_BIN} -c -do simulation/modelsim/${PROJECT_NAME}_run_msim_rtl_verilog.do -do exit
 
+compile_mem: $(MEMRES)
+
+%.mem: $(MEMDEP) 
+	${ASMC} -t mem -o $@ -f $<
+
 gentable:
 	$(foreach x,$(GENTABLE_CSV),$(call execute-gentable,./$(x)))
 
+clean:
+	rm -f $(MEMRES)
+
+.PHONY: clean