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@@ -6,15 +6,19 @@ QUARTUS_MAP = ${QUARTUS_DIR}/bin/quartus_map --read_settings_files=on --write_se
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MODELSIM_GUI = ${QUARTUS_DIR}/bin/quartus_sh -t "${QUARTUS_DIR}/common/tcl/internal/nativelink/qnativesim.tcl" --rtl_sim "${PROJECT_NAME}" "${PROJECT_NAME}"
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MODELSIM_BIN = ${MODELSIM_DIR}/bin/vsim
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+GENTABLE_BIN = python3 tools/gen_sv.py
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+ASMC = python3 tools/asm_compiler.py
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+
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+MEMDEP = memory/risc8_test.asm
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+MEMRES = $(MEMDEP:.asm=.mem)
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# Genreate sv case table from csv
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-GENSV = python3 tools/gen_sv.py
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GENTABLE_CSV = src/risc/controller.csv
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define execute-gentable
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-$(GENSV) $(1) $(1:.csv=.sv)
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+$(GENTABLE_BIN) $(1) $(1:.csv=.sv)
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endef
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-analysis:
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+analysis: compile_mem
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${QUARTUS_MAP} --analysis_and_elaboration
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synthesis:
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@@ -29,6 +33,15 @@ modelsim_gui:
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compile:
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${MODELSIM_BIN} -c -do simulation/modelsim/${PROJECT_NAME}_run_msim_rtl_verilog.do -do exit
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+compile_mem: $(MEMRES)
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+
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+%.mem: $(MEMDEP)
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+ ${ASMC} -t mem -o $@ -f $<
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+
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gentable:
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$(foreach x,$(GENTABLE_CSV),$(call execute-gentable,./$(x)))
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+clean:
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+ rm -f $(MEMRES)
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+
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+.PHONY: clean
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