Final report WIP

Finalised intro and goals section. Added instruction comp. and size graphs to results.

docs/final_report/1-abstract.tex

@@ -0,0 +1 @@
+% !TeX root = index.tex

docs/final_report/3-objectives.tex

@@ -1,3 +1,4 @@
+% !TeX root = index.tex
 \iffalse
 This chapter describes your Goals and Objectives. 
 Indicate how your work is intended to expand on previous historical work.
@@ -11,17 +12,27 @@ electrical or electronic apparatus or device within the bounds
 of the department's educational mandate.
 \fi
 
-OISC \texttt{MOVE} has many benefits from VLIW and SIMO or SIMT design, however there is a lack of research investigating and comparing more general purpose OISC \texttt{MOVE} 8bit processor with short instruction word and SISO (single instruction, single operation) configuration.  The main theory for building both architectures will be based on following resources \autocite{ong_ang_seng_2010,gilreath_laplante_2003,kong_ang_seng_adejo_2010,dharshana_balasubramanian_arun_2016}.
 
-RISC architecture will be mainly based on MIPS architecture explained in \autocite{harris_harris_2013}, except it is 8bit and would have multiple optimisations. 
-This project has three main motivations:
+This project can be classified as Design and Construction which explores alternative designs of processor architecture and microarchitecture. :
 \begin{enumerate}
-	\item Compare how well OISC \texttt{MOVE} architecture would perform in low performance microcontroller application comparing to equivalent RISC architecture.
 	\item Study and explore computer architectures, SystemVerilog and assembly languages. 
-	\item View an alternative method of using OISC \texttt{MOVE} as SISO architecture, comparing to more commonly implemented TTAs architectures that are either VLIW SIMO type or SIMT.
+	\item Compare how well OISC \texttt{MOVE} architecture would perform in low performance microcontroller application comparing to equivalent and most commonly used RISC architecture.
+	\item View an alternative method of using OISC \texttt{MOVE} in a SISO (single instruction, single operation) structure, comparing to more commonly implemented TTAs VLIW architectures that are either SIMO or SIMT structure.
 \end{enumerate}
 
 
+\subsection{RISC Processor}
+As this is aimed for low power and performance applications it will be 8bit word processor with four general purpose registers, structure is similar to MIPS.
+RISC architecture will be mainly based on MIPS architecture explained in \autocite{harris_harris_2013}, except it this RISC processor would have 8bit databus and would have multiple optimisations related to 8bit limits. Some minimalistic ideas was also from \autocite{gilreath_laplante_2003}.
+
+
+\subsection{OISC Processor}
+There are number of different implementations that uses only single instruction. OISC \texttt{MOVE} has many benefits from VLIW and SIMO or SIMT design, however there is a lack of research investigating and comparing more general purpose OISC \texttt{MOVE} 8bit processor with short instruction word and SISO configuration.  The main theory for building OISC architecture will be based on \autocite{gilreath_laplante_2003}.
+
+\subsection{Benchmark}
+This benchmark include different algorithms that are commonly used in 8bit microcontrollers, IoT devices or similar low power microprocessor applications.
+
+
 \iffalse
 This is just a list of research papers and relative context:
 \autocite{5936440} - Novel processor for Multiple Instruction Multiple Data packet triggered architecture for pipeline and parallel processing.

docs/final_report/4-theory.tex

@@ -1,3 +1,4 @@
+% !TeX root = index.tex
 \iffalse
 This chapter presents the background physical or electrical theory
 and on any analytical methods you will use to accomplish your goals.

docs/final_report/6-results.tex

@@ -1,3 +1,4 @@
+% !TeX root = index.tex
 \iffalse
 This chapter looks specifically at your results.
 * You measured some samples. 
@@ -67,6 +68,8 @@ Much higher logic components in RISC can be also explained more complicated regi
 
 \subsubsection{Number of instructions}
 
+
+
 \subsubsection{Instruction composition}
 Function composition was executed with following code:
 
@@ -100,6 +103,22 @@ setup:
 \end{lstlisting}
 \end{blockpage}
 
+Results are represented in figure \ref{fig:instr_comp}. 
+\begin{figure*}[t]
+	\centering
+	\includegraphics[width=\linewidth]{../tests/instr_comp.eps}
+	\caption{Graph of instruction composition for every benchmark program.}
+	\label{fig:instr_comp}
+\end{figure*}
+
+\subsubsection{Program space}
+Figure \ref{fig:program_size}
+\begin{colfigure}
+	\centering
+	\includegraphics[width=\linewidth]{../tests/program_size.eps}
+	\captionof{figure}{Bar graph showing effective size in bits each benchmark function is taking in program memeory.}
+	\label{fig:program_size}
+\end{colfigure}
 
 \subsection{Maximum clock frequency}
 

docs/final_report/7-conclusion.tex

@@ -1,3 +1,4 @@
+% !TeX root = index.tex
 \iffalse
 The final chapter is short and sweet, to the point:
  what did you really accomplish? 

docs/final_report/8-appendix.tex

@@ -1,4 +1,4 @@
-
+% !TeX root = index.tex
 
 \subsection{Processor instruction set tables}\label{subsec:instruction_sets}
 \arrayrulecolor{black}

docs/final_report/index.tex

@@ -37,6 +37,7 @@
 
 \usepackage[backend=bibtex,style=numeric,sorting=none]{biblatex}
 \addbibresource{references.bib}
+\renewcommand*{\bibfont}{\footnotesize}
 
 % Our base colours
 \definecolor{c1}{HTML}{ff7568} 
@@ -52,7 +53,6 @@
 }
 \lstset{language=asm, basicstyle=\ttfamily, commentstyle=\color{gray}, emphstyle={\color{darkred}}}
 
-
 % This enviroment ensures that structures like listing and tables are not broken between columns or pages.
 \newenvironment{blockpage}
 {\begin{center}\begin{minipage}[c]{\linewidth}}

docs/final_report/references.bib

@@ -46,7 +46,7 @@
 	year={2014}
 },
 
-@INPROCEEDINGS{dharshana_balasubramanian_arun_2016,
+@INPROCEEDINGS{7530376,
 	title={Encrypted computation on a one instruction set architecture},
 	DOI={10.1109/iccpct.2016.7530376},
 	journal={2016 International Conference on Circuit, Power and Computing Technologies (ICCPCT)},
@@ -54,7 +54,7 @@
 	year={2016}
 },
 
-@INPROCEEDINGS{ong_ang_seng_2010,
+@INPROCEEDINGS{5735103,
 	title={Implementation of (15, 9) Reed Solomon Minimal Instruction Set Computing on FPGA using Handel-C},
 	DOI={10.1109/iccaie.2010.5735103},
 	journal={2010 International Conference on Computer Applications and Industrial Electronics},
@@ -114,7 +114,7 @@
 	pages={13-16}
 },
 
-@INPROCEEDINGS{kong_ang_seng_adejo_2010,
+@INPROCEEDINGS{5735100,
 	title={Minimal Instruction Set FPGA AES processor using Handel},
 	DOI={10.1109/iccaie.2010.5735100},
 	journal={2010 International Conference on Computer Applications and Industrial Electronics},