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@@ -1,3 +1,4 @@
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+% !TeX root = index.tex
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\iffalse
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This chapter describes your Goals and Objectives.
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Indicate how your work is intended to expand on previous historical work.
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@@ -11,17 +12,27 @@ electrical or electronic apparatus or device within the bounds
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of the department's educational mandate.
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\fi
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-OISC \texttt{MOVE} has many benefits from VLIW and SIMO or SIMT design, however there is a lack of research investigating and comparing more general purpose OISC \texttt{MOVE} 8bit processor with short instruction word and SISO (single instruction, single operation) configuration. The main theory for building both architectures will be based on following resources \autocite{ong_ang_seng_2010,gilreath_laplante_2003,kong_ang_seng_adejo_2010,dharshana_balasubramanian_arun_2016}.
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-RISC architecture will be mainly based on MIPS architecture explained in \autocite{harris_harris_2013}, except it is 8bit and would have multiple optimisations.
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-This project has three main motivations:
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+This project can be classified as Design and Construction which explores alternative designs of processor architecture and microarchitecture. :
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\begin{enumerate}
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- \item Compare how well OISC \texttt{MOVE} architecture would perform in low performance microcontroller application comparing to equivalent RISC architecture.
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\item Study and explore computer architectures, SystemVerilog and assembly languages.
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- \item View an alternative method of using OISC \texttt{MOVE} as SISO architecture, comparing to more commonly implemented TTAs architectures that are either VLIW SIMO type or SIMT.
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+ \item Compare how well OISC \texttt{MOVE} architecture would perform in low performance microcontroller application comparing to equivalent and most commonly used RISC architecture.
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+ \item View an alternative method of using OISC \texttt{MOVE} in a SISO (single instruction, single operation) structure, comparing to more commonly implemented TTAs VLIW architectures that are either SIMO or SIMT structure.
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\end{enumerate}
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+\subsection{RISC Processor}
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+As this is aimed for low power and performance applications it will be 8bit word processor with four general purpose registers, structure is similar to MIPS.
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+RISC architecture will be mainly based on MIPS architecture explained in \autocite{harris_harris_2013}, except it this RISC processor would have 8bit databus and would have multiple optimisations related to 8bit limits. Some minimalistic ideas was also from \autocite{gilreath_laplante_2003}.
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+
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+
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+\subsection{OISC Processor}
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+There are number of different implementations that uses only single instruction. OISC \texttt{MOVE} has many benefits from VLIW and SIMO or SIMT design, however there is a lack of research investigating and comparing more general purpose OISC \texttt{MOVE} 8bit processor with short instruction word and SISO configuration. The main theory for building OISC architecture will be based on \autocite{gilreath_laplante_2003}.
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+
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+\subsection{Benchmark}
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+This benchmark include different algorithms that are commonly used in 8bit microcontrollers, IoT devices or similar low power microprocessor applications.
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+
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+
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\iffalse
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This is just a list of research papers and relative context:
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\autocite{5936440} - Novel processor for Multiple Instruction Multiple Data packet triggered architecture for pipeline and parallel processing.
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