New ROM

Reconstruced ROM to use M9K memory in fpga and use simulated version on
HDL simulation. Verilog macro 'SYNTHESIS' is added so code can be
corrected for simulated and synthesised cases.

.gitignore

@@ -1,7 +1,6 @@
 *.bak
 *.bak[0-9]*
 *.rpt
-*.mem
 *.xrf
 *.svo
 *.sft

Makefile

@@ -4,6 +4,7 @@ MODELSIM_DIR = /opt/altera/18.1/modelsim_ase
 PROJECT_NAME = UCL_project_y3
 MODELSIM_GUI = ${QUARTUS_DIR}/bin/quartus_sh -t "${QUARTUS_DIR}/common/tcl/internal/nativelink/qnativesim.tcl" --rtl_sim "${PROJECT_NAME}" "${PROJECT_NAME}"
 MODELSIM_BIN = ${MODELSIM_DIR}/bin/vsim
+QUARTUS_MACROS =  --set VERILOG_MACRO="SYNTHESIS=1"
 
 # OUTPUT FILES
 OUTPUTP = output_files/$(PROJECT_NAME)
@@ -15,10 +16,12 @@ TTY  ?= /dev/ttyUSB0
 BAUD ?= 9600
 
 GENTABLE_BIN = python3 tools/gen_sv.py
-ASMC = python3 tools/asm_compiler.py
+ASMC = python3 tools/risc8asm.py
 
+MEMSIZE ?= 4096
 MEMDEP := $(shell find memory -name '*.asm')
-MEMRES = $(MEMDEP:.asm=.mem)
+MEMSLICES = 0 1 2 3
+MEMRES = $(foreach i,$(MEMSLICES),$(MEMDEP:.asm=_$(i).mem)) $(foreach i,$(MEMSLICES),$(MEMDEP:.asm=_$(i).mif))
 
 VERILOG ?= $(wildcard src/*/*.sv) 
 
@@ -29,18 +32,18 @@ $(GENTABLE_BIN) $(1) $(1:.csv=.sv)
 endef
 
 analysis: compile_mem
-	${QUARTUS_DIR}/bin/quartus_map --read_settings_files=on --write_settings_files=off ${PROJECT_NAME} -c ${PROJECT_NAME} --analysis_and_elaboration
+	${QUARTUS_DIR}/bin/quartus_map --read_settings_files=on --write_settings_files=off ${QUARTUS_MACROS} ${PROJECT_NAME} -c ${PROJECT_NAME} --analysis_and_elaboration
 
 $(OUT_ASM): $(MEMDEP)
-	${QUARTUS_DIR}/bin/quartus_map --read_settings_files=on --write_settings_files=off ${PROJECT_NAME} -c ${PROJECT_NAME} 
-	${QUARTUS_DIR}/bin/quartus_fit --read_settings_files=off --write_settings_files=off ${PROJECT_NAME} -c ${PROJECT_NAME} 
-	${QUARTUS_DIR}/bin/quartus_asm --read_settings_files=off --write_settings_files=off ${PROJECT_NAME} -c ${PROJECT_NAME} 
+	${QUARTUS_DIR}/bin/quartus_map --read_settings_files=on --write_settings_files=off ${QUARTUS_MACROS} ${PROJECT_NAME} -c ${PROJECT_NAME} 
+	${QUARTUS_DIR}/bin/quartus_fit --read_settings_files=off --write_settings_files=off ${QUARTUS_MACROS} ${PROJECT_NAME} -c ${PROJECT_NAME} 
+	${QUARTUS_DIR}/bin/quartus_asm --read_settings_files=off --write_settings_files=off ${QUARTUS_MACROS} ${PROJECT_NAME} -c ${PROJECT_NAME} 
 
 $(OUT_STA): $(OUT_ASM)
 	${QUARTUS_DIR}/bin/quartus_sta ${PROJECT_NAME} -c ${PROJECT_NAME}
 
 eda: $(OUT_STA)
-	${QUARTUS_DIR}/bin/quartus_eda --read_settings_files=off --write_settings_files=off ${PROJECT_NAME} -c ${PROJECT_NAME} 
+	${QUARTUS_DIR}/bin/quartus_eda --read_settings_files=off --write_settings_files=off ${QUARTUS_MACROS} ${PROJECT_NAME} -c ${PROJECT_NAME} 
 
 program: $(OUT_ASM)
 	${QUARTUS_DIR}/bin/quartus_pgm -z -c $(JTAG) -m jtag -o "p;$(OUT_ASM)@1"
@@ -76,8 +79,17 @@ testbench: compile
 
 compile_mem: $(MEMRES)
 
+%_0.mem %_1.mem %_2.mem %_3.mem: %.asm
+	$(ASMC) -t mem -f $< -S $(words $(MEMSLICES)) -l $(MEMSIZE)
+
+%_0.mif %_1.mif %_2.mif %_3.mif: %.asm
+	$(ASMC) -t mif -f $< -S $(words $(MEMSLICES)) -l $(MEMSIZE)
+
 %.mem: %.asm
-	$(ASMC) -t mem -o $@ -f $<
+	$(ASMC) -t mem -o $@ -f $< -l $(MEMSIZE)
+
+%.mif: %.asm
+	$(ASMC) -t mif -o $@ -f $< -l $(MEMSIZE)
 
 clean:
 	rm -f $(MEMRES)

UCL_project_y3.qsf

@@ -55,10 +55,7 @@ set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH
 set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
 set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
 set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation
-set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH testbench_1 -section_id eda_simulation
-set_global_assignment -name EDA_TEST_BENCH_NAME testbench_1 -section_id eda_simulation
-set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id testbench_1
-set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME testbench_1 -section_id testbench_1
+set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH top_tb -section_id eda_simulation
 set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
 set_location_assignment PIN_P2 -to DRAM_ADDR[0]
 set_location_assignment PIN_L4 -to DRAM_ADDR[12]
@@ -119,7 +116,11 @@ set_location_assignment PIN_R8 -to CLK50
 set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
 set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
 set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
-set_global_assignment -name VERILOG_FILE src/blocks/alu.v
+set_global_assignment -name EDA_TEST_BENCH_NAME top_tb -section_id eda_simulation
+set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id top_tb
+set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME top_tb -section_id top_tb
+set_global_assignment -name EDA_TEST_BENCH_FILE src/top.sv -section_id top_tb
+set_global_assignment -name SYSTEMVERILOG_FILE src/blocks/rom.sv
 set_global_assignment -name SYSTEMVERILOG_FILE src/project.sv
 set_global_assignment -name SYSTEMVERILOG_FILE src/top.sv
 set_global_assignment -name VERILOG_FILE src/blocks/fifo.v
@@ -136,12 +137,5 @@ set_global_assignment -name SYSTEMVERILOG_FILE src/blocks/reg_file.sv
 set_global_assignment -name SYSTEMVERILOG_FILE src/blocks/memory.sv
 set_global_assignment -name QIP_FILE quartus/pll_clk.qip
 set_global_assignment -name SYSTEMVERILOG_FILE src/blocks/alu.sv
-set_global_assignment -name EDA_TEST_BENCH_FILE src/blocks/alu.sv -section_id testbench_1
-set_global_assignment -name EDA_TEST_BENCH_FILE src/blocks/instr_mem.sv -section_id testbench_1
-set_global_assignment -name EDA_TEST_BENCH_FILE src/blocks/memory.sv -section_id testbench_1
-set_global_assignment -name EDA_TEST_BENCH_FILE src/blocks/sdram_control.sv -section_id testbench_1
-set_global_assignment -name EDA_TEST_BENCH_FILE src/risc/general.sv -section_id testbench_1
-set_global_assignment -name EDA_TEST_BENCH_FILE src/risc/controller.sv -section_id testbench_1
-set_global_assignment -name EDA_TEST_BENCH_FILE src/risc/datapath.sv -section_id testbench_1
-set_global_assignment -name EDA_TEST_BENCH_FILE src/risc/cpu.sv -section_id testbench_1
+set_global_assignment -name QIP_FILE quartus/risc8_rom.qip
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

simulation/modelsim/UCL_project_y3_run_msim_rtl_verilog.do

@@ -9,9 +9,9 @@ vlog -sv -work work +incdir+/home/min/devel/fpga/ucl_project_y3/src/blocks {/hom
 vlog -sv -work work +incdir+/home/min/devel/fpga/ucl_project_y3/src/blocks {/home/min/devel/fpga/ucl_project_y3/src/blocks/uart.v}
 vlog -sv -work work +incdir+/home/min/devel/fpga/ucl_project_y3/quartus {/home/min/devel/fpga/ucl_project_y3/quartus/pll_clk.v}
 vlog -sv -work work +incdir+/home/min/devel/fpga/ucl_project_y3/db {/home/min/devel/fpga/ucl_project_y3/db/pll_clk_altpll.v}
+vlog -sv -work work +incdir+/home/min/devel/fpga/ucl_project_y3/src/blocks {/home/min/devel/fpga/ucl_project_y3/src/blocks/rom.sv}
 vlog -sv -work work +incdir+/home/min/devel/fpga/ucl_project_y3/src {/home/min/devel/fpga/ucl_project_y3/src/project.sv}
 vlog -sv -work work +incdir+/home/min/devel/fpga/ucl_project_y3/src/blocks {/home/min/devel/fpga/ucl_project_y3/src/blocks/sdram_control.sv}
-vlog -sv -work work +incdir+/home/min/devel/fpga/ucl_project_y3/src/blocks {/home/min/devel/fpga/ucl_project_y3/src/blocks/instr_mem.sv}
 vlog -sv -work work +incdir+/home/min/devel/fpga/ucl_project_y3/src/blocks {/home/min/devel/fpga/ucl_project_y3/src/blocks/reg_file.sv}
 vlog -sv -work work +incdir+/home/min/devel/fpga/ucl_project_y3/src/blocks {/home/min/devel/fpga/ucl_project_y3/src/blocks/alu.sv}
 vlog -sv -work work +incdir+/home/min/devel/fpga/ucl_project_y3/src {/home/min/devel/fpga/ucl_project_y3/src/top.sv}
@@ -20,16 +20,9 @@ vlog -sv -work work +incdir+/home/min/devel/fpga/ucl_project_y3/src/risc {/home/
 vlog -sv -work work +incdir+/home/min/devel/fpga/ucl_project_y3/src/risc {/home/min/devel/fpga/ucl_project_y3/src/risc/cpu.sv}
 vlog -sv -work work +incdir+/home/min/devel/fpga/ucl_project_y3/src/risc {/home/min/devel/fpga/ucl_project_y3/src/risc/controller.sv}
 
-vlog -sv -work work +incdir+/home/min/devel/fpga/ucl_project_y3/src/blocks {/home/min/devel/fpga/ucl_project_y3/src/blocks/alu.sv}
-vlog -sv -work work +incdir+/home/min/devel/fpga/ucl_project_y3/src/blocks {/home/min/devel/fpga/ucl_project_y3/src/blocks/instr_mem.sv}
-vlog -sv -work work +incdir+/home/min/devel/fpga/ucl_project_y3/src/blocks {/home/min/devel/fpga/ucl_project_y3/src/blocks/memory.sv}
-vlog -sv -work work +incdir+/home/min/devel/fpga/ucl_project_y3/src/blocks {/home/min/devel/fpga/ucl_project_y3/src/blocks/sdram_control.sv}
-vlog -sv -work work +incdir+/home/min/devel/fpga/ucl_project_y3/src/risc {/home/min/devel/fpga/ucl_project_y3/src/risc/general.sv}
-vlog -sv -work work +incdir+/home/min/devel/fpga/ucl_project_y3/src/risc {/home/min/devel/fpga/ucl_project_y3/src/risc/controller.sv}
-vlog -sv -work work +incdir+/home/min/devel/fpga/ucl_project_y3/src/risc {/home/min/devel/fpga/ucl_project_y3/src/risc/datapath.sv}
-vlog -sv -work work +incdir+/home/min/devel/fpga/ucl_project_y3/src/risc {/home/min/devel/fpga/ucl_project_y3/src/risc/cpu.sv}
+vlog -sv -work work +incdir+/home/min/devel/fpga/ucl_project_y3/src {/home/min/devel/fpga/ucl_project_y3/src/top.sv}
 
-vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs="+acc"  testbench_1
+vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs="+acc"  top_tb
 
 add wave *
 view structure

src/blocks/instr_mem.sv

@@ -6,7 +6,7 @@ module instr_rom(addr, instr);
 	input  wire [ADDR_WIDTH-1:0]   addr;
 	output reg  [WIDTH*OUTMUL-1:0] instr;
 	
-	initial $display("Instruction ROM %0dx%0dbit, size of %0dB loaded from %s ...", WIDTH, ADDR_WIDTH, LENGTH*WIDTH/8, FILE);
+	initial $display("Instruction ROM %0dx%0dbit, size of %0dB loaded from %s", WIDTH, ADDR_WIDTH, LENGTH*WIDTH/8, FILE);
 	logic [WIDTH-1:0] rom [LENGTH-1:0];
 	initial if(FILE != "") $readmemh(FILE, rom);
 	initial begin

src/blocks/instr_mem_wr.sv

@@ -0,0 +1,18 @@
+//module instr_rom_wr(clk, addr, instr, wr_en, wr_data);
+module rom(addr, q);
+	parameter PROGRAM="";
+	parameter WIDTH=8, SIZE=1024;
+	parameter ADDR_WIDTH = $clog2(SIZE);
+	
+	//input  reg 	clk, wr_en;
+	//input reg [WIDTH-1:0] wr_data;
+	input  wire [ADDR_WIDTH-1:0]   addr;
+	output  reg  [WIDTH-1:0] q;
+	
+	logic [WIDTH-1:0] rom [ADDR_WIDTH-1:0];
+	initial $readmemh(PROGRAM, rom);
+	//always_ff@(posedge clk) if(wr) rom[addr] <= instr; 	
+
+	always_comb q[WIDTH-1:0] = rom[addr];
+endmodule
+

src/blocks/rom.sv

@@ -0,0 +1,143 @@
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+
+
+module m9k_rom (
+	address,
+	clock,
+	q);
+
+	parameter PROGRAM="";
+	parameter NAME="";
+
+	input	[9:0]  address;
+	input	  clock;
+	output	[7:0]  q;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+	tri1	  clock;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+	wire [7:0] sub_wire0;
+	wire [7:0] q = sub_wire0[7:0];
+	
+	initial $display("Initialising ROM Memory: %s", PROGRAM);
+
+	altsyncram	altsyncram_component (
+				.address_a (address),
+				.clock0 (clock),
+				.q_a (sub_wire0),
+				.aclr0 (1'b0),
+				.aclr1 (1'b0),
+				.address_b (1'b1),
+				.addressstall_a (1'b0),
+				.addressstall_b (1'b0),
+				.byteena_a (1'b1),
+				.byteena_b (1'b1),
+				.clock1 (1'b1),
+				.clocken0 (1'b1),
+				.clocken1 (1'b1),
+				.clocken2 (1'b1),
+				.clocken3 (1'b1),
+				.data_a ({8{1'b1}}),
+				.data_b (1'b1),
+				.eccstatus (),
+				.q_b (),
+				.rden_a (1'b1),
+				.rden_b (1'b1),
+				.wren_a (1'b0),
+				.wren_b (1'b0));
+	defparam
+		altsyncram_component.address_aclr_a = "NONE",
+		altsyncram_component.clock_enable_input_a = "BYPASS",
+		altsyncram_component.clock_enable_output_a = "BYPASS",
+		altsyncram_component.init_file = PROGRAM,
+		altsyncram_component.intended_device_family = "Cyclone IV E",
+		altsyncram_component.lpm_hint = {"ENABLE_RUNTIME_MOD=YES,INSTANCE_NAME=", NAME},
+		altsyncram_component.lpm_type = "altsyncram",
+		altsyncram_component.numwords_a = 1024,
+		altsyncram_component.operation_mode = "ROM",
+		altsyncram_component.outdata_aclr_a = "NONE",
+		altsyncram_component.outdata_reg_a = "UNREGISTERED",
+		altsyncram_component.ram_block_type = "M9K",
+		altsyncram_component.widthad_a = 10,
+		altsyncram_component.width_a = 8,
+		altsyncram_component.width_byteena_a = 1;
+
+endmodule 
+
+module pseudo_rom(addr, clk, q);
+	parameter PROGRAM="";
+	
+	input  reg 	clk;
+	input  wire [9:0] addr;
+	output  reg [7:0] q;
+	
+	initial $display("Initialising ROM Memory: %s", PROGRAM);
+	
+	reg [9:0] addr0;
+	logic [7:0] rom [2**10:0];
+	initial $readmemh(PROGRAM, rom);
+	always_ff@(posedge clk) addr0 <= addr; 	
+	assign q[7:0] = rom[addr0];
+
+endmodule
+
+module rom (
+	address,
+	clock,
+	q);
+	parameter PROGRAM="";
+
+	input	reg [11:0]  address;
+	input	clock;
+	output	reg [31:0]  q;
+	
+	reg [31:0]  qn;
+	
+	reg [9:0] addr0, addr1, addr2, addr3;
+	reg [11:0] a3, a2, a1;
+	reg [7:0] q0, q1, q2, q3;
+	reg [1:0] ar;
+	always_ff@(posedge clock) ar <= address[1:0];
+
+	always_comb begin
+		a3 = address + 3;
+		a2 = address + 2;
+		a1 = address + 1;
+		// Dividing by 4
+		addr0 = a3[11:2];
+		addr1 = a2[11:2];
+		addr2 = a1[11:2];
+		addr3 = address[11:2];
+		
+		case(ar)
+			2'b00: qn = {q3, q2, q1, q0};
+			2'b01: qn = {q0, q3, q2, q1};
+			2'b10: qn = {q1, q0, q3, q2};
+			2'b11: qn = {q2, q1, q0, q3};
+		endcase
+		q = qn;
+	end
+	//always_ff@(posedge clock) q <= qn;
+
+	`ifdef SYNTHESIS
+		m9k_rom#({PROGRAM, "_0.mif"}, "rom0") rom0(addr0, clock, q0);
+		m9k_rom#({PROGRAM, "_1.mif"}, "rom1") rom1(addr1, clock, q1);
+		m9k_rom#({PROGRAM, "_2.mif"}, "rom2") rom2(addr2, clock, q2);
+		m9k_rom#({PROGRAM, "_3.mif"}, "rom3") rom3(addr3, clock, q3);
+	`else
+		pseudo_rom#({PROGRAM, "_0.mem"}) rom0(addr0, clock, q0);
+		pseudo_rom#({PROGRAM, "_1.mem"}) rom1(addr1, clock, q1);
+		pseudo_rom#({PROGRAM, "_2.mem"}) rom2(addr2, clock, q2);
+		pseudo_rom#({PROGRAM, "_3.mem"}) rom3(addr3, clock, q3);
+	`endif
+
+endmodule
+
+

src/project.sv

@@ -30,7 +30,7 @@ module com_block(
 
 	// IO
 	output reg  [7:0]	leds,
-	input  wire  [3:0]	switches,
+	input  wire [3:0]	switches,
 	output wire			uart0_tx,
 	input  wire			uart0_rx,
 	input  wire			key1
@@ -38,32 +38,55 @@ module com_block(
 
 	/* UART */
 	reg [2:0] uart0_reg;
+	reg received;
 	reg uart0_transmit;
 	reg [7:0] tx_byte, rx_byte;
 	// Clock divide = 1e6 / (9600 * 4)
-	uart#(.CLOCK_DIVIDE(26)) uart0(
+	//uart#(.CLOCK_DIVIDE(26)) uart0(
+	uart#(.CLOCK_DIVIDE(1302)) uart0(
 			.clk(clk), 
 			.rst(rst), 
 			.rx(uart0_rx),
 			.tx(uart0_tx),
 			.tx_byte(tx_byte),
 			.rx_byte(rx_byte),
-			.received(uart0_reg[0]),
+			.received(received),
 			.is_receiving(uart0_reg[1]),
 			.is_transmitting(uart0_reg[2]),
 			.transmit(uart0_transmit)
 	);
-
+	
+	
+	//reg [7:0] reset_str [7];
+	//reg [2:0] reset_seq;
+	//always_comb begin
+	//		reset_str[0] = 8'h72;
+	//		reset_str[1] = 8'h65;
+	//		reset_str[2] = 8'h73;
+	//		reset_str[3] = 8'h65;
+	//		reset_str[4] = 8'h74;
+	//		reset_str[5] = 8'h2e;
+	//		reset_str[6] = 8'h10;
+	//end
+	
 	always_ff@(posedge clk) begin
-		if(addr == 8'h06) leds <= in_data;
+		if(rst) begin 
+			//reset_seq <= 0;
+			leds <= 'b0000_0000;
+		end
+		//else if(~uart0_reg[2] && reset_seq != 7) reset_seq <= reset_seq + 1;
+		else if(addr == 8'h06) leds <= in_data;
 	end
 
 	always_comb begin
-		uart0_transmit = (addr == 8'h05) ? 1 : 0;
-		tx_byte = in_data;
+		//tx_byte = 8'h23;
+		//uart0_transmit = 1;
+		uart0_transmit = (addr == 8'h05) || (received);
+		tx_byte = (received) ? rx_byte : in_data;
+		//tx_byte = in_data;
 		case(addr)
-			8'h04: out_data = {5'b0, uart0_reg};
-			8'h05: out_data = {5'b0, uart0_reg};
+			8'h04: out_data = {6'b0, uart0_reg};
+			8'h05: out_data = {6'b0, uart0_reg};
 			8'h07: out_data = {4'b0, switches};
 			default: out_data = 0;
 		endcase
@@ -76,7 +99,7 @@ module sdram_block(
 	// SDRAM Control
 	input [23:0]	ram_addr,
 	input [15:0] 	ram_wr_data,
-	output  [15:0] 	ram_rd_data,
+	output[15:0] 	ram_rd_data,
 	input 			ram_wr_en,
 	input			ram_rd_en,
 	output			ram_busy,

src/risc/controller.csv

@@ -32,7 +32,7 @@
      BGT,   ALU_NONE,   SB_IMM,         0,  SR_NONE,      0,      0,(cdi.alu_comp[2:1] == 'b01)?1:3,SO_MEML , ST_SKIP,(cdi.alu_comp[2:1] == 'b01)?PC_IMM2:PC_NONE
      BGE,   ALU_NONE,   SB_IMM,         0,  SR_NONE,      0,      0,(cdi.alu_comp[2]|cdi.alu_comp[1])?1:3,SO_MEML , ST_SKIP,(cdi.alu_comp[2]|cdi.alu_comp[1])?PC_IMM2:PC_NONE
       BZ,   ALU_NONE,  SB_NONE,         0,  SR_NONE,      0,      0,         0,SO_MEML , ST_SKIP, PC_NONE 
-    CALL,   ALU_NONE,  SB_NONE,         0,  SR_NONE,      0,      1,         1,SO_MEML ,  ST_SUB,  PC_IMM 
+    CALL,   ALU_NONE,  SB_NONE,         0,  SR_NONE,      0,      1,         2,SO_MEML ,  ST_SUB,  PC_IMM 
      RET,   ALU_NONE,  SB_NONE,         0,  SR_NONE,      1,      0,         2,SO_MEML ,  ST_ADD,  PC_MEM 
     JUMP,   ALU_NONE,  SB_NONE,         0,  SR_NONE,      0,      0,         1,SO_MEML , ST_NONE,  PC_IMM
     RETI,   ALU_NONE,  SB_NONE,         0,  SR_NONE,      1,      0,         2,SO_MEML ,  ST_SUB,  PC_MEM 

src/risc/controller.sv

@@ -1,4 +1,6 @@
-`define ADDOP
+`ifndef SYNTHESIS
+	`define ADDOP
+`endif
 
 import risc8_pkg::*;
 import alu_pkg::*;
@@ -13,10 +15,12 @@ module controller8(
 	assign cdi.a2		= e_reg_addr'(instr[1:0]);
 	assign cdi.a3 		= cdi.a1; // Assuming destination always first operand
 	
-	`ifdef ADDOP 
-	e_instr op;
+	`ifdef ADDOP
+		initial $display("Control adding 'op' reg");
+		e_instr op;
 	`endif
 
+
 	// generated table
     always_comb begin
     casez(instr)

src/risc/cpu.sv

@@ -16,19 +16,11 @@ import alu_pkg::*;
 //endmodule
 
 module risc8_cpu(processor_port port);
-	parameter PROGRAM="";
 	reg [31:0] instr; // Fetching 4x8bit instruction
 	reg [15:0] pc; // Instruction memory is 16bit in length
-	initial $display("RISC8 program: %s", PROGRAM);	
-	instr_rom #(.FILE(PROGRAM),
-				.LENGTH(256),
-				.OUTMUL(4),
-				.ADDR_WIDTH(16)
-		) rom0 (pc, instr);
-	
-	//risc8_cpu cpu0(port.clk, port.rst, instr, imm, pc,
-	//		port.ram_addr, mem_wr, port.ram_wr_data, port.ram_rd_data);
 	
+	rom#("../../memory/risc8") rom_block0(pc[11:0],  port.clk, instr);	
+
 	risc8_cdi cdi0();
 	controller8 ctrl0(
 			.instr(instr[7:0]),

src/risc/datapath.sv

@@ -65,27 +65,27 @@ module datapath8(
 	word pc_off; // Program counter offset
 	reg [15:0] pcn, pca; // Program Counter Previous, to add
 	always_ff@(posedge clk) begin
-			if(rst) pc <= '0; 
+			if(rst) pc <= 0; 
 			else pc <= pcn;
 	end
 	
 	always_comb begin
 		bconst = 0;  // FIXME: temporary
-		case(cdi.pcop)
-			PC_NONE: pca = pc;
-			PC_MEM : pca = mem_rd;
-			PC_IMM : pca = {imm[7:0], imm[15:8]};
-			PC_IMM2: pca = {imm[15:8], imm[23:16]};
-			default: pca = pc;
-		endcase
-		//pca = (bconst) ? {imm[7:0], imm[15:8]} : pc;
 		pc_off = { 
 			5'b0000_0, 
 			cdi.isize[0]&cdi.isize[1], 
 			cdi.isize[0]^cdi.isize[1], 
 			(~cdi.isize[1]&~cdi.isize[0])|(cdi.isize[1]&~cdi.isize[0])
 		}; // Adding 1 to 2bit value.
-		pcn = pca + pc_off;
+		case(cdi.pcop)
+			PC_NONE: pcn = pc + pc_off;
+			PC_MEM : pcn = mem_rd;
+			PC_IMM : pcn = {imm[7:0], imm[15:8]};
+			PC_IMM2: pcn = {imm[15:8], imm[23:16]};
+			default: pcn = pc;
+		endcase
+		//pca = (bconst) ? {imm[7:0], imm[15:8]} : pc;
+		//pcn = pca + pc_off;
 	end
 	
 	word interrupt_flag;
@@ -141,6 +141,8 @@ module datapath8(
 	// COM Write
 	assign com_wr = (cdi.selo == SO_COM) ? r1 : '0;
 	assign com_addr = imm[7:0];
+	//assign com_addr = 8'h06;
+	//assign com_wr = pc[7:0];
 
 	assign srcA = r1;
 	always_comb begin

src/top.sv

@@ -28,6 +28,12 @@ module top(
 	output [1:0] 	DRAM_BA		// Bank Address
 	);
 	
+	`ifdef SYNTHESIS
+		initial $display("Assuming this is synthesis");
+	`else
+		initial $display("Assuming this is simulation");
+	`endif
+
 	assign rst = ~KEY[0];
 	
 	/* Clocks */
@@ -37,11 +43,14 @@ module top(
 	
 	pll_clk pll_clk0 (
 			.inclk0(CLK50),
-			.areset(rst),
+			.areset(0),
 			.c0(fclk),
 			.c1(mclk),
 			.c2(aclk)
 	);
+	//clk_dive#(28'd50) clk_div_mclk(CLK50, mclk);
+	//assign mclk = ~KEY[1];	
+	//assign mclk = CLK50;	
 
 	wire [23:0]	ram_addr;
     wire [15:0] ram_wr_data;
@@ -51,7 +60,7 @@ module top(
     wire  		ram_busy;
 	wire  		ram_rd_ready;
 	wire  		ram_rd_ack;
-
+	
 	sdram_block sdram0(
 		.mclk(mclk), 
 		.fclk(fclk), 
@@ -116,3 +125,73 @@ module top(
 
 endmodule
 
+
+module clk_dive(clock_in,clock_out);
+input clock_in; // input clock on FPGA
+output clock_out; // output clock after dividing the input clock by divisor
+reg[27:0] counter=28'd0;
+parameter DIVISOR = 28'd2;
+always @(posedge clock_in)
+begin
+ counter <= counter + 28'd1;
+ if(counter>=(DIVISOR-1))
+  counter <= 28'd0;
+end
+assign clock_out = (counter<DIVISOR/2)?1'b0:1'b1;
+endmodule
+
+`timescale 1ns/1ns
+module top_tb;
+
+	logic 		 CLK50;		// Clock 50MHz
+	logic [3:0]	 SWITCH;		// 4 Dip switches
+	logic [1:0]	 KEY;		// 2 Keys
+	wire  [7:0]	 LED;		// 8 LEDs
+	logic 		 RX;			// UART Receive
+	logic 		 TX;			// UART Transmit
+	wire  [15:0] DRAM_DQ;	// Data
+	logic [12:0] DRAM_ADDR;	// Address
+	logic [1:0]	 DRAM_DQM;	// Byte Data Mask
+	logic  		 DRAM_CLK;	// Clock
+	logic  		 DRAM_CKE;	// Clock Enable
+	logic  		 DRAM_WE_N;	// Write Enable
+	logic  		 DRAM_CAS_N; // Column Address Strobe
+	logic  		 DRAM_RAS_N; // Row Address Strobe
+	logic  		 DRAM_CS_N;	// Chip Select
+	logic [1:0]  DRAM_BA;		// Bank Address
+
+	top top0(
+				CLK50,		
+				SWITCH,	
+				KEY,		
+				LED,		
+				RX,		
+				TX,		
+				DRAM_DQ,	
+				DRAM_ADDR,	
+				DRAM_DQM,	
+				DRAM_CLK,	
+				DRAM_CKE,	
+				DRAM_WE_N,	
+				DRAM_CAS_N,
+				DRAM_RAS_N,
+				DRAM_CS_N,	
+				DRAM_BA	
+				);
+
+	initial begin
+			CLK50 = 0;
+			KEY[0] = 0;
+			KEY[1] = 1;
+			SWITCH = 4'b0110;
+			RX = 0;
+
+			#1100ns;
+			KEY[0] = 1;
+			#10us;
+			$stop;
+	end
+	initial forever #10ns CLK50 = ~CLK50;
+	
+
+endmodule