controller.sv 21 KB

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  1. `ifndef SYNTHESIS
  2. `define ADDOP
  3. `endif
  4. import risc8_pkg::*;
  5. import alu_pkg::*;
  6. module controller8(
  7. input word instr,
  8. risc8_cdi.control cdi,
  9. output reg mem_wr, mem_rd
  10. );
  11. // Instruction decoding
  12. assign cdi.a1 = e_reg_addr'(instr[3:2]);
  13. assign cdi.a2 = e_reg_addr'(instr[1:0]);
  14. assign cdi.a3 = cdi.a1; // Assuming destination always first operand
  15. `ifdef ADDOP
  16. initial $display("Control adding 'op' reg");
  17. e_instr op;
  18. `endif
  19. // generated table
  20. always_comb begin
  21. casez(instr)
  22. CPY0 : begin
  23. cdi.alu_op = ALU_NONE;
  24. cdi.selb = SB_IMM;
  25. cdi.rw_en = 1;
  26. cdi.selr = SR_IMM;
  27. mem_rd = 0;
  28. mem_wr = 0;
  29. cdi.isize = 1;
  30. cdi.selo = SO_MEML;
  31. cdi.stackop = ST_SKIP;
  32. cdi.pcop = PC_NONE;
  33. `ifdef ADDOP
  34. op = CPY0;
  35. `endif
  36. end
  37. CPY1 : begin
  38. cdi.alu_op = ALU_NONE;
  39. cdi.selb = SB_IMM;
  40. cdi.rw_en = 1;
  41. cdi.selr = SR_IMM;
  42. mem_rd = 0;
  43. mem_wr = 0;
  44. cdi.isize = 1;
  45. cdi.selo = SO_MEML;
  46. cdi.stackop = ST_SKIP;
  47. cdi.pcop = PC_NONE;
  48. `ifdef ADDOP
  49. op = CPY1;
  50. `endif
  51. end
  52. CPY2 : begin
  53. cdi.alu_op = ALU_NONE;
  54. cdi.selb = SB_IMM;
  55. cdi.rw_en = 1;
  56. cdi.selr = SR_IMM;
  57. mem_rd = 0;
  58. mem_wr = 0;
  59. cdi.isize = 1;
  60. cdi.selo = SO_MEML;
  61. cdi.stackop = ST_SKIP;
  62. cdi.pcop = PC_NONE;
  63. `ifdef ADDOP
  64. op = CPY2;
  65. `endif
  66. end
  67. CPY3 : begin
  68. cdi.alu_op = ALU_NONE;
  69. cdi.selb = SB_IMM;
  70. cdi.rw_en = 1;
  71. cdi.selr = SR_IMM;
  72. mem_rd = 0;
  73. mem_wr = 0;
  74. cdi.isize = 1;
  75. cdi.selo = SO_MEML;
  76. cdi.stackop = ST_SKIP;
  77. cdi.pcop = PC_NONE;
  78. `ifdef ADDOP
  79. op = CPY3;
  80. `endif
  81. end
  82. MOVE : begin
  83. cdi.alu_op = ALU_NONE;
  84. cdi.selb = SB_NONE;
  85. cdi.rw_en = 1;
  86. cdi.selr = SR_REG;
  87. mem_rd = 0;
  88. mem_wr = 0;
  89. cdi.isize = 0;
  90. cdi.selo = SO_MEML;
  91. cdi.stackop = ST_SKIP;
  92. cdi.pcop = PC_NONE;
  93. `ifdef ADDOP
  94. op = MOVE;
  95. `endif
  96. end
  97. ADD : begin
  98. cdi.alu_op = ALU_ADD;
  99. cdi.selb = SB_REG;
  100. cdi.rw_en = 1;
  101. cdi.selr = SR_ALUL;
  102. mem_rd = 0;
  103. mem_wr = 0;
  104. cdi.isize = 0;
  105. cdi.selo = SO_MEML;
  106. cdi.stackop = ST_SKIP;
  107. cdi.pcop = PC_NONE;
  108. `ifdef ADDOP
  109. op = ADD;
  110. `endif
  111. end
  112. SUB : begin
  113. cdi.alu_op = ALU_SUB;
  114. cdi.selb = SB_REG;
  115. cdi.rw_en = 1;
  116. cdi.selr = SR_ALUL;
  117. mem_rd = 0;
  118. mem_wr = 0;
  119. cdi.isize = 0;
  120. cdi.selo = SO_MEML;
  121. cdi.stackop = ST_SKIP;
  122. cdi.pcop = PC_NONE;
  123. `ifdef ADDOP
  124. op = SUB;
  125. `endif
  126. end
  127. AND : begin
  128. cdi.alu_op = ALU_AND;
  129. cdi.selb = SB_REG;
  130. cdi.rw_en = 1;
  131. cdi.selr = SR_ALUL;
  132. mem_rd = 0;
  133. mem_wr = 0;
  134. cdi.isize = 0;
  135. cdi.selo = SO_MEML;
  136. cdi.stackop = ST_SKIP;
  137. cdi.pcop = PC_NONE;
  138. `ifdef ADDOP
  139. op = AND;
  140. `endif
  141. end
  142. OR : begin
  143. cdi.alu_op = ALU_OR;
  144. cdi.selb = SB_REG;
  145. cdi.rw_en = 1;
  146. cdi.selr = SR_ALUL;
  147. mem_rd = 0;
  148. mem_wr = 0;
  149. cdi.isize = 0;
  150. cdi.selo = SO_MEML;
  151. cdi.stackop = ST_SKIP;
  152. cdi.pcop = PC_NONE;
  153. `ifdef ADDOP
  154. op = OR;
  155. `endif
  156. end
  157. XOR : begin
  158. cdi.alu_op = ALU_XOR;
  159. cdi.selb = SB_REG;
  160. cdi.rw_en = 1;
  161. cdi.selr = SR_ALUL;
  162. mem_rd = 0;
  163. mem_wr = 0;
  164. cdi.isize = 0;
  165. cdi.selo = SO_MEML;
  166. cdi.stackop = ST_SKIP;
  167. cdi.pcop = PC_NONE;
  168. `ifdef ADDOP
  169. op = XOR;
  170. `endif
  171. end
  172. MUL : begin
  173. cdi.alu_op = ALU_MUL;
  174. cdi.selb = SB_REG;
  175. cdi.rw_en = 1;
  176. cdi.selr = SR_ALUL;
  177. mem_rd = 0;
  178. mem_wr = 0;
  179. cdi.isize = 0;
  180. cdi.selo = SO_MEML;
  181. cdi.stackop = ST_SKIP;
  182. cdi.pcop = PC_NONE;
  183. `ifdef ADDOP
  184. op = MUL;
  185. `endif
  186. end
  187. DIV : begin
  188. cdi.alu_op = ALU_DIV;
  189. cdi.selb = SB_REG;
  190. cdi.rw_en = 1;
  191. cdi.selr = SR_ALUL;
  192. mem_rd = 0;
  193. mem_wr = 0;
  194. cdi.isize = 0;
  195. cdi.selo = SO_MEML;
  196. cdi.stackop = ST_SKIP;
  197. cdi.pcop = PC_NONE;
  198. `ifdef ADDOP
  199. op = DIV;
  200. `endif
  201. end
  202. BR : begin
  203. cdi.alu_op = ALU_NONE;
  204. cdi.selb = SB_NONE;
  205. cdi.rw_en = 0;
  206. cdi.selr = SR_NONE;
  207. mem_rd = 0;
  208. mem_wr = 0;
  209. cdi.isize = 2;
  210. cdi.selo = SO_MEML;
  211. cdi.stackop = ST_SKIP;
  212. cdi.pcop = PC_NONE;
  213. `ifdef ADDOP
  214. op = BR;
  215. `endif
  216. end
  217. SLL : begin
  218. cdi.alu_op = ALU_SL;
  219. cdi.selb = SB_REG;
  220. cdi.rw_en = 1;
  221. cdi.selr = SR_ALUL;
  222. mem_rd = 0;
  223. mem_wr = 0;
  224. cdi.isize = 0;
  225. cdi.selo = SO_MEML;
  226. cdi.stackop = ST_SKIP;
  227. cdi.pcop = PC_NONE;
  228. `ifdef ADDOP
  229. op = SLL;
  230. `endif
  231. end
  232. SRL : begin
  233. cdi.alu_op = ALU_SR;
  234. cdi.selb = SB_REG;
  235. cdi.rw_en = 1;
  236. cdi.selr = SR_ALUL;
  237. mem_rd = 0;
  238. mem_wr = 0;
  239. cdi.isize = 0;
  240. cdi.selo = SO_MEML;
  241. cdi.stackop = ST_SKIP;
  242. cdi.pcop = PC_NONE;
  243. `ifdef ADDOP
  244. op = SRL;
  245. `endif
  246. end
  247. SRA : begin
  248. cdi.alu_op = ALU_RA;
  249. cdi.selb = SB_REG;
  250. cdi.rw_en = 1;
  251. cdi.selr = SR_ALUL;
  252. mem_rd = 0;
  253. mem_wr = 0;
  254. cdi.isize = 0;
  255. cdi.selo = SO_MEML;
  256. cdi.stackop = ST_SKIP;
  257. cdi.pcop = PC_NONE;
  258. `ifdef ADDOP
  259. op = SRA;
  260. `endif
  261. end
  262. SRAS : begin
  263. cdi.alu_op = ALU_RAS;
  264. cdi.selb = SB_REG;
  265. cdi.rw_en = 1;
  266. cdi.selr = SR_ALUL;
  267. mem_rd = 0;
  268. mem_wr = 0;
  269. cdi.isize = 0;
  270. cdi.selo = SO_MEML;
  271. cdi.stackop = ST_SKIP;
  272. cdi.pcop = PC_NONE;
  273. `ifdef ADDOP
  274. op = SRAS;
  275. `endif
  276. end
  277. LWHI : begin
  278. cdi.alu_op = ALU_NONE;
  279. cdi.selb = SB_NONE;
  280. cdi.rw_en = 1;
  281. cdi.selr = SR_MEMH;
  282. mem_rd = 1;
  283. mem_wr = 0;
  284. cdi.isize = 3;
  285. cdi.selo = SO_MEML;
  286. cdi.stackop = ST_SKIP;
  287. cdi.pcop = PC_NONE;
  288. `ifdef ADDOP
  289. op = LWHI;
  290. `endif
  291. end
  292. SWHI : begin
  293. cdi.alu_op = ALU_NONE;
  294. cdi.selb = SB_NONE;
  295. cdi.rw_en = 0;
  296. cdi.selr = SR_NONE;
  297. mem_rd = 0;
  298. mem_wr = 0;
  299. cdi.isize = 0;
  300. cdi.selo = SO_MEMH;
  301. cdi.stackop = ST_SKIP;
  302. cdi.pcop = PC_NONE;
  303. `ifdef ADDOP
  304. op = SWHI;
  305. `endif
  306. end
  307. LWLO : begin
  308. cdi.alu_op = ALU_NONE;
  309. cdi.selb = SB_NONE;
  310. cdi.rw_en = 1;
  311. cdi.selr = SR_MEML;
  312. mem_rd = 1;
  313. mem_wr = 0;
  314. cdi.isize = 3;
  315. cdi.selo = SO_MEML;
  316. cdi.stackop = ST_SKIP;
  317. cdi.pcop = PC_NONE;
  318. `ifdef ADDOP
  319. op = LWLO;
  320. `endif
  321. end
  322. SWLO : begin
  323. cdi.alu_op = ALU_NONE;
  324. cdi.selb = SB_NONE;
  325. cdi.rw_en = 0;
  326. cdi.selr = SR_NONE;
  327. mem_rd = 0;
  328. mem_wr = 1;
  329. cdi.isize = 3;
  330. cdi.selo = SO_MEML;
  331. cdi.stackop = ST_SKIP;
  332. cdi.pcop = PC_NONE;
  333. `ifdef ADDOP
  334. op = SWLO;
  335. `endif
  336. end
  337. INC : begin
  338. cdi.alu_op = ALU_ADD;
  339. cdi.selb = SB_1;
  340. cdi.rw_en = 1;
  341. cdi.selr = SR_ALUL;
  342. mem_rd = 0;
  343. mem_wr = 0;
  344. cdi.isize = 0;
  345. cdi.selo = SO_MEML;
  346. cdi.stackop = ST_SKIP;
  347. cdi.pcop = PC_NONE;
  348. `ifdef ADDOP
  349. op = INC;
  350. `endif
  351. end
  352. DEC : begin
  353. cdi.alu_op = ALU_SUB;
  354. cdi.selb = SB_1;
  355. cdi.rw_en = 1;
  356. cdi.selr = SR_ALUL;
  357. mem_rd = 0;
  358. mem_wr = 0;
  359. cdi.isize = 0;
  360. cdi.selo = SO_MEML;
  361. cdi.stackop = ST_SKIP;
  362. cdi.pcop = PC_NONE;
  363. `ifdef ADDOP
  364. op = DEC;
  365. `endif
  366. end
  367. GETAH : begin
  368. cdi.alu_op = ALU_NONE;
  369. cdi.selb = SB_NONE;
  370. cdi.rw_en = 1;
  371. cdi.selr = SR_ALUH;
  372. mem_rd = 0;
  373. mem_wr = 0;
  374. cdi.isize = 0;
  375. cdi.selo = SO_MEML;
  376. cdi.stackop = ST_SKIP;
  377. cdi.pcop = PC_NONE;
  378. `ifdef ADDOP
  379. op = GETAH;
  380. `endif
  381. end
  382. GETIF : begin
  383. cdi.alu_op = ALU_NONE;
  384. cdi.selb = SB_NONE;
  385. cdi.rw_en = 1;
  386. cdi.selr = SR_INTR;
  387. mem_rd = 0;
  388. mem_wr = 0;
  389. cdi.isize = 0;
  390. cdi.selo = SO_MEML;
  391. cdi.stackop = ST_SKIP;
  392. cdi.pcop = PC_NONE;
  393. `ifdef ADDOP
  394. op = GETIF;
  395. `endif
  396. end
  397. PUSH : begin
  398. cdi.alu_op = ALU_NONE;
  399. cdi.selb = SB_NONE;
  400. cdi.rw_en = 0;
  401. cdi.selr = SR_NONE;
  402. mem_rd = 0;
  403. mem_wr = 1;
  404. cdi.isize = 0;
  405. cdi.selo = SO_MEML;
  406. cdi.stackop = ST_SUB;
  407. cdi.pcop = PC_NONE;
  408. `ifdef ADDOP
  409. op = PUSH;
  410. `endif
  411. end
  412. POP : begin
  413. cdi.alu_op = ALU_NONE;
  414. cdi.selb = SB_NONE;
  415. cdi.rw_en = 1;
  416. cdi.selr = SR_MEML;
  417. mem_rd = 1;
  418. mem_wr = 0;
  419. cdi.isize = 0;
  420. cdi.selo = SO_MEML;
  421. cdi.stackop = ST_ADD;
  422. cdi.pcop = PC_NONE;
  423. `ifdef ADDOP
  424. op = POP;
  425. `endif
  426. end
  427. COM : begin
  428. cdi.alu_op = ALU_NONE;
  429. cdi.selb = SB_NONE;
  430. cdi.rw_en = 1;
  431. cdi.selr = SR_COM;
  432. mem_rd = 0;
  433. mem_wr = 0;
  434. cdi.isize = 1;
  435. cdi.selo = SO_COM;
  436. cdi.stackop = ST_SKIP;
  437. cdi.pcop = PC_NONE;
  438. `ifdef ADDOP
  439. op = COM;
  440. `endif
  441. end
  442. SETI : begin
  443. cdi.alu_op = ALU_NONE;
  444. cdi.selb = SB_NONE;
  445. cdi.rw_en = 0;
  446. cdi.selr = SR_NONE;
  447. mem_rd = 0;
  448. mem_wr = 0;
  449. cdi.isize = 0;
  450. cdi.selo = SO_MEML;
  451. cdi.stackop = ST_SKIP;
  452. cdi.pcop = PC_NONE;
  453. `ifdef ADDOP
  454. op = SETI;
  455. `endif
  456. end
  457. BEQ : begin
  458. cdi.alu_op = ALU_NONE;
  459. cdi.selb = SB_IMM;
  460. cdi.rw_en = 0;
  461. cdi.selr = SR_NONE;
  462. mem_rd = 0;
  463. mem_wr = 0;
  464. cdi.isize = (cdi.alu_comp[2:1] == 'b10)?1:3;
  465. cdi.selo = SO_MEML;
  466. cdi.stackop = ST_SKIP;
  467. cdi.pcop = (cdi.alu_comp[2:1] == 'b10)?PC_IMM2:PC_NONE;
  468. `ifdef ADDOP
  469. op = BEQ;
  470. `endif
  471. end
  472. BGT : begin
  473. cdi.alu_op = ALU_NONE;
  474. cdi.selb = SB_IMM;
  475. cdi.rw_en = 0;
  476. cdi.selr = SR_NONE;
  477. mem_rd = 0;
  478. mem_wr = 0;
  479. cdi.isize = (cdi.alu_comp[2:1] == 'b01)?1:3;
  480. cdi.selo = SO_MEML;
  481. cdi.stackop = ST_SKIP;
  482. cdi.pcop = (cdi.alu_comp[2:1] == 'b01)?PC_IMM2:PC_NONE;
  483. `ifdef ADDOP
  484. op = BGT;
  485. `endif
  486. end
  487. BGE : begin
  488. cdi.alu_op = ALU_NONE;
  489. cdi.selb = SB_IMM;
  490. cdi.rw_en = 0;
  491. cdi.selr = SR_NONE;
  492. mem_rd = 0;
  493. mem_wr = 0;
  494. cdi.isize = (cdi.alu_comp[2]|cdi.alu_comp[1])?1:3;
  495. cdi.selo = SO_MEML;
  496. cdi.stackop = ST_SKIP;
  497. cdi.pcop = (cdi.alu_comp[2]|cdi.alu_comp[1])?PC_IMM2:PC_NONE;
  498. `ifdef ADDOP
  499. op = BGE;
  500. `endif
  501. end
  502. BZ : begin
  503. cdi.alu_op = ALU_NONE;
  504. cdi.selb = SB_NONE;
  505. cdi.rw_en = 0;
  506. cdi.selr = SR_NONE;
  507. mem_rd = 0;
  508. mem_wr = 0;
  509. cdi.isize = 0;
  510. cdi.selo = SO_MEML;
  511. cdi.stackop = ST_SKIP;
  512. cdi.pcop = PC_NONE;
  513. `ifdef ADDOP
  514. op = BZ;
  515. `endif
  516. end
  517. CALL : begin
  518. cdi.alu_op = ALU_NONE;
  519. cdi.selb = SB_NONE;
  520. cdi.rw_en = 0;
  521. cdi.selr = SR_NONE;
  522. mem_rd = 0;
  523. mem_wr = 1;
  524. cdi.isize = 1;
  525. cdi.selo = SO_MEML;
  526. cdi.stackop = ST_SUB;
  527. cdi.pcop = PC_IMM;
  528. `ifdef ADDOP
  529. op = CALL;
  530. `endif
  531. end
  532. RET : begin
  533. cdi.alu_op = ALU_NONE;
  534. cdi.selb = SB_NONE;
  535. cdi.rw_en = 0;
  536. cdi.selr = SR_NONE;
  537. mem_rd = 1;
  538. mem_wr = 0;
  539. cdi.isize = 2;
  540. cdi.selo = SO_MEML;
  541. cdi.stackop = ST_ADD;
  542. cdi.pcop = PC_MEM;
  543. `ifdef ADDOP
  544. op = RET;
  545. `endif
  546. end
  547. JUMP : begin
  548. cdi.alu_op = ALU_NONE;
  549. cdi.selb = SB_NONE;
  550. cdi.rw_en = 0;
  551. cdi.selr = SR_NONE;
  552. mem_rd = 0;
  553. mem_wr = 0;
  554. cdi.isize = 1;
  555. cdi.selo = SO_MEML;
  556. cdi.stackop = ST_NONE;
  557. cdi.pcop = PC_IMM;
  558. `ifdef ADDOP
  559. op = JUMP;
  560. `endif
  561. end
  562. RETI : begin
  563. cdi.alu_op = ALU_NONE;
  564. cdi.selb = SB_NONE;
  565. cdi.rw_en = 0;
  566. cdi.selr = SR_NONE;
  567. mem_rd = 1;
  568. mem_wr = 0;
  569. cdi.isize = 2;
  570. cdi.selo = SO_MEML;
  571. cdi.stackop = ST_SUB;
  572. cdi.pcop = PC_MEM;
  573. `ifdef ADDOP
  574. op = RETI;
  575. `endif
  576. end
  577. CLC : begin
  578. cdi.alu_op = ALU_NONE;
  579. cdi.selb = SB_NONE;
  580. cdi.rw_en = 0;
  581. cdi.selr = SR_NONE;
  582. mem_rd = 0;
  583. mem_wr = 0;
  584. cdi.isize = 0;
  585. cdi.selo = SO_MEML;
  586. cdi.stackop = ST_SKIP;
  587. cdi.pcop = PC_NONE;
  588. `ifdef ADDOP
  589. op = CLC;
  590. `endif
  591. end
  592. SETC : begin
  593. cdi.alu_op = ALU_NONE;
  594. cdi.selb = SB_NONE;
  595. cdi.rw_en = 0;
  596. cdi.selr = SR_NONE;
  597. mem_rd = 0;
  598. mem_wr = 0;
  599. cdi.isize = 0;
  600. cdi.selo = SO_MEML;
  601. cdi.stackop = ST_SKIP;
  602. cdi.pcop = PC_NONE;
  603. `ifdef ADDOP
  604. op = SETC;
  605. `endif
  606. end
  607. CLS : begin
  608. cdi.alu_op = ALU_NONE;
  609. cdi.selb = SB_NONE;
  610. cdi.rw_en = 0;
  611. cdi.selr = SR_NONE;
  612. mem_rd = 0;
  613. mem_wr = 0;
  614. cdi.isize = 0;
  615. cdi.selo = SO_MEML;
  616. cdi.stackop = ST_SKIP;
  617. cdi.pcop = PC_NONE;
  618. `ifdef ADDOP
  619. op = CLS;
  620. `endif
  621. end
  622. SETS : begin
  623. cdi.alu_op = ALU_NONE;
  624. cdi.selb = SB_NONE;
  625. cdi.rw_en = 0;
  626. cdi.selr = SR_NONE;
  627. mem_rd = 0;
  628. mem_wr = 0;
  629. cdi.isize = 0;
  630. cdi.selo = SO_MEML;
  631. cdi.stackop = ST_SKIP;
  632. cdi.pcop = PC_NONE;
  633. `ifdef ADDOP
  634. op = SETS;
  635. `endif
  636. end
  637. SSETS : begin
  638. cdi.alu_op = ALU_NONE;
  639. cdi.selb = SB_NONE;
  640. cdi.rw_en = 0;
  641. cdi.selr = SR_NONE;
  642. mem_rd = 0;
  643. mem_wr = 0;
  644. cdi.isize = 0;
  645. cdi.selo = SO_MEML;
  646. cdi.stackop = ST_SKIP;
  647. cdi.pcop = PC_NONE;
  648. `ifdef ADDOP
  649. op = SSETS;
  650. `endif
  651. end
  652. CLN : begin
  653. cdi.alu_op = ALU_NONE;
  654. cdi.selb = SB_NONE;
  655. cdi.rw_en = 0;
  656. cdi.selr = SR_NONE;
  657. mem_rd = 0;
  658. mem_wr = 0;
  659. cdi.isize = 0;
  660. cdi.selo = SO_MEML;
  661. cdi.stackop = ST_SKIP;
  662. cdi.pcop = PC_NONE;
  663. `ifdef ADDOP
  664. op = CLN;
  665. `endif
  666. end
  667. SETN : begin
  668. cdi.alu_op = ALU_NONE;
  669. cdi.selb = SB_NONE;
  670. cdi.rw_en = 0;
  671. cdi.selr = SR_NONE;
  672. mem_rd = 0;
  673. mem_wr = 0;
  674. cdi.isize = 0;
  675. cdi.selo = SO_MEML;
  676. cdi.stackop = ST_SKIP;
  677. cdi.pcop = PC_NONE;
  678. `ifdef ADDOP
  679. op = SETN;
  680. `endif
  681. end
  682. SSETN : begin
  683. cdi.alu_op = ALU_NONE;
  684. cdi.selb = SB_NONE;
  685. cdi.rw_en = 0;
  686. cdi.selr = SR_NONE;
  687. mem_rd = 0;
  688. mem_wr = 0;
  689. cdi.isize = 0;
  690. cdi.selo = SO_MEML;
  691. cdi.stackop = ST_SKIP;
  692. cdi.pcop = PC_NONE;
  693. `ifdef ADDOP
  694. op = SSETN;
  695. `endif
  696. end
  697. RJUMP : begin
  698. cdi.alu_op = ALU_NONE;
  699. cdi.selb = SB_NONE;
  700. cdi.rw_en = 0;
  701. cdi.selr = SR_NONE;
  702. mem_rd = 0;
  703. mem_wr = 0;
  704. cdi.isize = 2;
  705. cdi.selo = SO_MEML;
  706. cdi.stackop = ST_SKIP;
  707. cdi.pcop = PC_NONE;
  708. `ifdef ADDOP
  709. op = RJUMP;
  710. `endif
  711. end
  712. RBWI : begin
  713. cdi.alu_op = ALU_NONE;
  714. cdi.selb = SB_NONE;
  715. cdi.rw_en = 0;
  716. cdi.selr = SR_NONE;
  717. mem_rd = 0;
  718. mem_wr = 0;
  719. cdi.isize = 1;
  720. cdi.selo = SO_MEML;
  721. cdi.stackop = ST_SKIP;
  722. cdi.pcop = PC_NONE;
  723. `ifdef ADDOP
  724. op = RBWI;
  725. `endif
  726. end
  727. default: begin
  728. cdi.alu_op = ALU_NONE;
  729. cdi.selb = SB_NONE;
  730. cdi.rw_en = 0;
  731. cdi.selr = SR_NONE;
  732. mem_rd = 0;
  733. mem_wr = 0;
  734. cdi.isize = 0;
  735. cdi.selo = SO_MEML;
  736. cdi.stackop = ST_SKIP;
  737. cdi.pcop = PC_NONE;
  738. end
  739. endcase
  740. end
  741. // generated table end
  742. endmodule
  743. `timescale 1ns / 1ns
  744. module controller8_tb;
  745. word instr;
  746. risc8_cdi cdi();
  747. logic mem_wr, mem_rd;
  748. controller8 c0(instr, cdi, mem_wr, mem_rd);
  749. initial begin
  750. instr = 8'b0000_0000;
  751. cdi.alu_comp = 3'b000;
  752. #10ns;
  753. instr = 8'b0000_0100;
  754. #10ns;
  755. instr = 8'b0001_0001;
  756. #10ns;
  757. instr = 8'b0010_0001;
  758. #10ns;
  759. instr = 8'b1111_1111;
  760. #10ns;
  761. end
  762. endmodule