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+ 12 - 0
docs/final_report/3-objectives.tex

@@ -29,6 +29,18 @@ RISC architecture will be mainly based on MIPS architecture explained in \autoci
 \subsection{OISC Processor}
 \subsection{OISC Processor}
 There are number of different implementations that uses only single instruction. OISC \texttt{MOVE} has many benefits from VLIW and SIMO or SIMT design, however there is a lack of research investigating and comparing more general purpose OISC \texttt{MOVE} 8bit processor with short instruction word and SISO configuration.  The main theory for building OISC architecture will be based on \autocite{gilreath_laplante_2003}.
 There are number of different implementations that uses only single instruction. OISC \texttt{MOVE} has many benefits from VLIW and SIMO or SIMT design, however there is a lack of research investigating and comparing more general purpose OISC \texttt{MOVE} 8bit processor with short instruction word and SISO configuration.  The main theory for building OISC architecture will be based on \autocite{gilreath_laplante_2003}.
 
 
+\subsection{Design Criteria}
+In order for fair comparison between both architectures, a common design criteria:
+\begin{description}
+	\item[$\bullet$] Minimal instruction size
+	\item[$\bullet$] Minimalistic design
+	\item[$\bullet$] 8bit data bus width
+	\item[$\bullet$] 16bit ROM address width
+	\item[$\bullet$] 24bit RAM address width
+	\item[$\bullet$] 16bit RAM word size
+\end{description}
+When constructing these points, time and equipment resources were taken into consideration. 
+
 \subsection{Benchmark}
 \subsection{Benchmark}
 This benchmark include different algorithms that are commonly used in 8bit microcontrollers, IoT devices or similar low power microprocessor applications.
 This benchmark include different algorithms that are commonly used in 8bit microcontrollers, IoT devices or similar low power microprocessor applications.
 
 

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docs/final_report/4-theory.tex


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docs/final_report/5-methods.tex


+ 2 - 1
docs/final_report/8-appendix.tex

@@ -182,4 +182,5 @@ INTRE& Set interrupt entry pointer & 2 \\\hline
 	REG0 & Get value from general purpose register 0 \\
 	REG0 & Get value from general purpose register 0 \\
 	REG1 & Get value from general purpose register 1 \\
 	REG1 & Get value from general purpose register 1 \\
 	
 	
-\end{longtable}	
+\end{longtable}	
+

binární
docs/final_report/index.pdf


+ 6 - 5
docs/final_report/index.tex

@@ -13,6 +13,7 @@
 \usepackage{enumitem}
 \usepackage{enumitem}
 \usepackage{lipsum}
 \usepackage{lipsum}
 \usepackage{listings}
 \usepackage{listings}
+\usepackage{pdflscape}
 
 
 
 
 \usepackage{tabularx}
 \usepackage{tabularx}
@@ -116,23 +117,23 @@
 	
 	
 	\section{Introduction}\label{sec:introduction}
 	\section{Introduction}\label{sec:introduction}
 	\input{2-introduction.tex}
 	\input{2-introduction.tex}
-
+	\vfill\pagebreak
 	\section{Goals and Objectives}\label{sec:objectives}
 	\section{Goals and Objectives}\label{sec:objectives}
 	\input{3-objectives.tex}
 	\input{3-objectives.tex}
 
 
 	\section{Theory and Analytical Bases}\label{sec:theory}
 	\section{Theory and Analytical Bases}\label{sec:theory}
 	\input{4-theory.tex}
 	\input{4-theory.tex}
-
+	\vfill\pagebreak
+	
 	\section{Technical Method}\label{sec:methods}
 	\section{Technical Method}\label{sec:methods}
 	\input{5-methods.tex}
 	\input{5-methods.tex}
-	\pagebreak
+	\vfill\pagebreak
 	\section{Results and Analysis}\label{sec:results}
 	\section{Results and Analysis}\label{sec:results}
 	\input{6-results.tex}
 	\input{6-results.tex}
 
 
 	\section{Conclusion}\label{sec:conclusion}
 	\section{Conclusion}\label{sec:conclusion}
 	\input{7-conclusion.tex}
 	\input{7-conclusion.tex}
-
-	\section{References}
+	\vfill\pagebreak
 	\printbibliography
 	\printbibliography
 	\onecolumn
 	\onecolumn
 	\section{Appendix}\label{sec:appendix}
 	\section{Appendix}\label{sec:appendix}

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docs/resources/datapath.dia


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