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@@ -29,6 +29,18 @@ RISC architecture will be mainly based on MIPS architecture explained in \autoci
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\subsection{OISC Processor}
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There are number of different implementations that uses only single instruction. OISC \texttt{MOVE} has many benefits from VLIW and SIMO or SIMT design, however there is a lack of research investigating and comparing more general purpose OISC \texttt{MOVE} 8bit processor with short instruction word and SISO configuration. The main theory for building OISC architecture will be based on \autocite{gilreath_laplante_2003}.
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+\subsection{Design Criteria}
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+In order for fair comparison between both architectures, a common design criteria:
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+\begin{description}
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+ \item[$\bullet$] Minimal instruction size
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+ \item[$\bullet$] Minimalistic design
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+ \item[$\bullet$] 8bit data bus width
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+ \item[$\bullet$] 16bit ROM address width
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+ \item[$\bullet$] 24bit RAM address width
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+ \item[$\bullet$] 16bit RAM word size
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+\end{description}
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+When constructing these points, time and equipment resources were taken into consideration.
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+
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\subsection{Benchmark}
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This benchmark include different algorithms that are commonly used in 8bit microcontrollers, IoT devices or similar low power microprocessor applications.
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