Shell basename fix

Makefile

@@ -36,7 +36,7 @@ VSIM_ARGS = -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lns
 ## also includes subdirectories that has syntax
 ## src/{MOD_NAME}/{MOD_NAME}.sv or src/{MOD_NAME}/include.sv
 ###
-VERILOG_SRC=$(foreach SRC,$(sort $(dir $(wildcard ./src/*/*.sv))),$(wildcard $(SRC)$(shell basename $(SRC)).sv $(SRC)include.sv)) $(wildcard ./src/*.sv)
+VERILOG_SRC=$(foreach SRC,$(sort $(dir $(wildcard ./src/*/*.sv))),$(wildcard $(SRC)$(basename $(SRC)).sv $(SRC)include.sv)) $(wildcard ./src/*.sv)
 $(info VERILOG_SRC=$(VERILOG_SRC))
 SIM_DIR ?= ./simulation/modelsim