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@@ -36,7 +36,7 @@ VSIM_ARGS = -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lns
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## also includes subdirectories that has syntax
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## src/{MOD_NAME}/{MOD_NAME}.sv or src/{MOD_NAME}/include.sv
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###
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-VERILOG_SRC=$(foreach SRC,$(sort $(dir $(wildcard ./src/*/*.sv))),$(wildcard $(SRC)$(shell basename $(SRC)).sv $(SRC)include.sv)) $(wildcard ./src/*.sv)
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+VERILOG_SRC=$(foreach SRC,$(sort $(dir $(wildcard ./src/*/*.sv))),$(wildcard $(SRC)$(basename $(SRC)).sv $(SRC)include.sv)) $(wildcard ./src/*.sv)
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$(info VERILOG_SRC=$(VERILOG_SRC))
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SIM_DIR ?= ./simulation/modelsim
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