ucl_project_y3/UCL_project_y3.qsf

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#
# Copyright (C) 2018  Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Intel Program License 
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
# Intel and sold by Intel or its authorized distributors.  Please
# refer to the applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
# Date created = 13:15:52  September 19, 2019
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
#		UCL_project_y3_assignment_defaults.qdf
#    If this file doesn't exist, see file:
#		assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
#    file is updated automatically by the Quartus Prime software
#    and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #


set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name DEVICE EP4CE22F17C6
set_global_assignment -name TOP_LEVEL_ENTITY top
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 18.1.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:15:52  SEPTEMBER 19, 2019"
set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (SystemVerilog)"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "SYSTEMVERILOG HDL" -section_id eda_simulation
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation
set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH testbench_1 -section_id eda_simulation
set_global_assignment -name EDA_TEST_BENCH_NAME testbench_1 -section_id eda_simulation
set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id testbench_1
set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME testbench_1 -section_id testbench_1
set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
set_location_assignment PIN_P2 -to DRAM_ADDR[0]
set_location_assignment PIN_L4 -to DRAM_ADDR[12]
set_location_assignment PIN_N1 -to DRAM_ADDR[11]
set_location_assignment PIN_N2 -to DRAM_ADDR[10]
set_location_assignment PIN_N5 -to DRAM_ADDR[1]
set_location_assignment PIN_N6 -to DRAM_ADDR[2]
set_location_assignment PIN_M8 -to DRAM_ADDR[3]
set_location_assignment PIN_P8 -to DRAM_ADDR[4]
set_location_assignment PIN_T7 -to DRAM_ADDR[5]
set_location_assignment PIN_N8 -to DRAM_ADDR[6]
set_location_assignment PIN_T6 -to DRAM_ADDR[7]
set_location_assignment PIN_R1 -to DRAM_ADDR[8]
set_location_assignment PIN_P1 -to DRAM_ADDR[9]
set_location_assignment PIN_G2 -to DRAM_DQ[0]
set_location_assignment PIN_G1 -to DRAM_DQ[1]
set_location_assignment PIN_L8 -to DRAM_DQ[2]
set_location_assignment PIN_K5 -to DRAM_DQ[3]
set_location_assignment PIN_K2 -to DRAM_DQ[4]
set_location_assignment PIN_J2 -to DRAM_DQ[5]
set_location_assignment PIN_J1 -to DRAM_DQ[6]
set_location_assignment PIN_R7 -to DRAM_DQ[7]
set_location_assignment PIN_T4 -to DRAM_DQ[8]
set_location_assignment PIN_T2 -to DRAM_DQ[9]
set_location_assignment PIN_T3 -to DRAM_DQ[10]
set_location_assignment PIN_R3 -to DRAM_DQ[11]
set_location_assignment PIN_R5 -to DRAM_DQ[12]
set_location_assignment PIN_P3 -to DRAM_DQ[13]
set_location_assignment PIN_N3 -to DRAM_DQ[14]
set_location_assignment PIN_K1 -to DRAM_DQ[15]
set_location_assignment PIN_P6 -to DRAM_CS_N
set_location_assignment PIN_R4 -to DRAM_CLK
set_location_assignment PIN_L7 -to DRAM_CKE
set_location_assignment PIN_M6 -to DRAM_BA[0]
set_location_assignment PIN_M7 -to DRAM_BA[1]
set_location_assignment PIN_L1 -to DRAM_CAS_N
set_location_assignment PIN_C2 -to DRAM_WE_N
set_location_assignment PIN_L2 -to DRAM_RAS_N
set_location_assignment PIN_R6 -to DRAM_DQM[0]
set_location_assignment PIN_T5 -to DRAM_DQM[1]
set_location_assignment PIN_L3 -to LED[7]
set_location_assignment PIN_D3 -to RX
set_location_assignment PIN_C3 -to TX
set_location_assignment PIN_A15 -to LED[0]
set_location_assignment PIN_A13 -to LED[1]
set_location_assignment PIN_B13 -to LED[2]
set_location_assignment PIN_A11 -to LED[3]
set_location_assignment PIN_D1 -to LED[4]
set_location_assignment PIN_F3 -to LED[5]
set_location_assignment PIN_B1 -to LED[6]
set_location_assignment PIN_E1 -to KEY[1]
set_location_assignment PIN_J15 -to KEY[0]
set_location_assignment PIN_M1 -to SWITCH[0]
set_location_assignment PIN_T8 -to SWITCH[1]
set_location_assignment PIN_B9 -to SWITCH[2]
set_location_assignment PIN_M15 -to SWITCH[3]
set_location_assignment PIN_R8 -to CLK50
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name VERILOG_FILE src/blocks/alu.v
set_global_assignment -name SYSTEMVERILOG_FILE src/project.sv
set_global_assignment -name SYSTEMVERILOG_FILE src/top.sv
set_global_assignment -name VERILOG_FILE src/blocks/fifo.v
set_global_assignment -name SYSTEMVERILOG_FILE src/blocks/sdram_control.sv
set_global_assignment -name SYSTEMVERILOG_FILE src/risc/general.sv
set_global_assignment -name SYSTEMVERILOG_FILE src/risc/datapath.sv
set_global_assignment -name SYSTEMVERILOG_FILE src/risc/cpu.sv
set_global_assignment -name SYSTEMVERILOG_FILE src/risc/controller.sv
set_global_assignment -name MIF_FILE memory/rom_test.mem
set_global_assignment -name SYSTEMVERILOG_FILE src/blocks/clk_div.sv
set_global_assignment -name VERILOG_FILE src/blocks/uart.v
set_global_assignment -name SYSTEMVERILOG_FILE src/blocks/instr_mem.sv
set_global_assignment -name SYSTEMVERILOG_FILE src/blocks/reg_file.sv
set_global_assignment -name SYSTEMVERILOG_FILE src/blocks/memory.sv
set_global_assignment -name QIP_FILE quartus/pll_clk.qip
set_global_assignment -name SYSTEMVERILOG_FILE src/blocks/alu.sv
set_global_assignment -name EDA_TEST_BENCH_FILE src/blocks/alu.sv -section_id testbench_1
set_global_assignment -name EDA_TEST_BENCH_FILE src/blocks/instr_mem.sv -section_id testbench_1
set_global_assignment -name EDA_TEST_BENCH_FILE src/blocks/memory.sv -section_id testbench_1
set_global_assignment -name EDA_TEST_BENCH_FILE src/blocks/sdram_control.sv -section_id testbench_1
set_global_assignment -name EDA_TEST_BENCH_FILE src/risc/general.sv -section_id testbench_1
set_global_assignment -name EDA_TEST_BENCH_FILE src/risc/controller.sv -section_id testbench_1
set_global_assignment -name EDA_TEST_BENCH_FILE src/risc/datapath.sv -section_id testbench_1
set_global_assignment -name EDA_TEST_BENCH_FILE src/risc/cpu.sv -section_id testbench_1
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top