Min
49689e242c
Do not simulate rst signal
|
6 gadi atpakaļ | |
|---|---|---|
| .. | ||
| UCL_project_y3_run_msim_rtl_verilog.do | 6 gadi atpakaļ | |
| modelsim.ini | 6 gadi atpakaļ | |
| risc8_tb_wave.do | 6 gadi atpakaļ | |
| risc_tb_wave.do | 6 gadi atpakaļ | |
| top_compile.do | 6 gadi atpakaļ | |
| top_wave.do | 6 gadi atpakaļ | |
| wave.do | 6 gadi atpakaļ | |