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- % !TeX root = index.tex
- \iffalse
- The final chapter is short and sweet, to the point:
- what did you really accomplish?
- What significant result can you claim and how it differs from anything done before.
- How well did you meet your goal?
- Now step out one level, then another indicating the impact your work will have on the literature and on future endeavours.
- * Start with the specifics and end with the general.
- * Summarise key result; mention limitations, note anything unexpected.
- \fi
- In this paper, two novel RISC and OISC-MOVE architectures were designed and implemented on a FPGA. Logic element requirements, power consumption, maximum frequency were tested. Benchmark programs execution times were used to compare these two processors and investigate OISC-MOVE advantages. It was shown that power consumption differences are insignificant, RISC managed to reach 40\% higher maximum frequency at 75-70MHz, however due to a timing design issue with OISC. OISC required 51.7\% less logic elements to implement on FPGA. Benchmarks showed that OISC took 71\% longer to execute on average while requiring 41.71\% more instruction space.
- This project has sucessfully covered its goals in studying architectures and investigating an alternative OISC implementation. Results show that proposed implementation of OISC-MOVE may be only suitable for microprocessor application with very strict logic element limit.
- RISC processor has been shown to be superior in tests, however it has more optimised implementation. Further research is needed to investigate OISC-MOVE performance with multiple data and instruction buses to match RISC complexity.
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