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- @INPROCEEDINGS{5403730, author={ {Su Wang} and {Suying Yao} and {Wei Guo} and {Jizeng Wei}}, booktitle={Proceedings of the 2009 12th International Symposium on Integrated Circuits}, title={An instruction redundancy removal method on a transport triggered architecture processor}, year={2009}, volume={}, number={}, pages={602-604}, doi={}, ISSN={2325-0631}, month={Dec},}
- @INPROCEEDINGS{6855236, author={B. {Rister} and P. {Jääskeläinen} and O. {Silvén} and J. {Hannuksela} and J. R. {Cavallaro}}, booktitle={2014 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP)}, title={Parallel programming of a symmetric transport-triggered architecture with applications in flexible LDPC encoding}, year={2014}, volume={}, number={}, pages={8380-8384}, doi={10.1109/ICASSP.2014.6855236}}
- @INPROCEEDINGS{922340, author={P. {Hamalainen} and M. {Hannikainen} and T. {Hamalainen} and H. {Corporaal} and J. {Saarvinen}}, booktitle={ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196)}, title={Implementation of encryption algorithms on transport triggered architectures}, year={2001}, volume={4}, number={}, pages={726-729 vol. 4}, doi={10.1109/ISCAS.2001.922340}}
- @INPROCEEDINGS{4595596, author={L. {Jiang} and Y. {Zhu} and Y. {Wei}}, booktitle={2008 International Conference on Embedded Software and Systems}, title={Software Pipelining with Minimal Loop Overhead on Transport Triggered Architecture}, year={2008}, volume={}, number={}, pages={451-458}, doi={10.1109/ICESS.2008.18}}
- @INPROCEEDINGS{1207041, author={T. {Pionteck} and A. {Garcia} and L. D. {Kabulepa} and M. {Glesner}}, booktitle={14th IEEE International Workshop on Rapid Systems Prototyping, 2003. Proceedings.}, title={Hardware evaluation of low power communication mechanisms for transport-triggered architectures}, year={2003}, volume={}, number={}, pages={141-147}, doi={10.1109/IWRSP.2003.1207041}}
- @INPROCEEDINGS{6972455, author={T. {Viitanen} and H. {Kultala} and P. {Jääskeläinen} and J. {Takala}}, booktitle={2014 International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES)}, title={Heuristics for greedy transport triggered architecture interconnect exploration}, year={2014}, volume={}, number={}, pages={1-7}, doi={10.1145/2656106.2656123}}
- @INPROCEEDINGS{7363689, author={J. {Multanen} and T. {Viitanen} and H. {Linjamäki} and H. {Kultala} and P. {Jääskeläinen} and J. {Takala} and L. {Koskinen} and J. {Simonsson} and H. {Berg} and K. {Raiskila} and T. {Zetterman}}, booktitle={2015 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS)}, title={Power optimizations for transport triggered SIMD processors}, year={2015}, volume={}, number={}, pages={303-309}, doi={10.1109/SAMOS.2015.7363689}}
- @INPROCEEDINGS{8425389, author={P. {Jääskeläinen} and A. {Tervo} and G. {Payá Vayá} and T. {Viitanen} and N. {Behmann} and J. {Takala} and H. {Blume}}, booktitle={2018 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)}, title={Transport-Triggered Soft Cores}, year={2018}, volume={}, number={}, pages={83-90}, doi={10.1109/IPDPSW.2018.00022}}
- @INPROCEEDINGS{8682289, author={J. {Žádník} and J. {Takala}}, booktitle={ICASSP 2019 - 2019 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP)}, title={Low-power Programmable Processor for Fast Fourier Transform Based on Transport Triggered Architecture}, year={2019}, volume={}, number={}, pages={1423-1427}, doi={10.1109/ICASSP.2019.8682289}}
- @INPROCEEDINGS{8573494, author={M. {Safarpour} and I. {Hautala} and O. {Silvén}}, booktitle={2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)}, title={An Embedded Programmable Processor for Compressive Sensing Applications}, year={2018}, volume={}, number={}, pages={1-5}, doi={10.1109/NORCHIP.2018.8573494}}
- @INPROCEEDINGS{4627144, author={J. {Wei} and W. {Guo} and J. {Sun} and Y. {Yao}}, booktitle={2008 International Conference on Embedded Software and Systems Symposia}, title={Program Compression Based on Arithmetic Coding on Transport Triggered Architecture}, year={2008}, volume={}, number={}, pages={126-131}, doi={10.1109/ICESS.Symposia.2008.9}}
- @INPROCEEDINGS{5936440, author={F. {Adamec} and T. {Fryza}}, booktitle={Proceedings of 21st International Conference Radioelektronika 2011}, title={Introduction to the new Packet Triggered Architecture for pipelined and parallel data processing}, year={2011}, volume={}, number={}, pages={1-4}, doi={10.1109/RADIOELEK.2011.5936440}}
- @INPROCEEDINGS{1213033, author={J. {Heikkinen} and T. {Rantanen} and A. {Cilio} and J. {Takala} and H. {Corporaal}}, booktitle={The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, 2003. Proceedings.}, title={Evaluating template-based instruction compression on transport triggered architectures}, doi={10.1109/IWSOC.2003.1213033}, year={2003}, volume={}, number={}, pages={192-195},}
- @INPROCEEDINGS{1511285, author={P. {Salmela} and T. {Jarvinen} and J. {Takala} and T. {Sipila}}, booktitle={International Symposium on Signals, Circuits and Systems, 2005. ISSCS 2005.}, title={Scalable FIR filtering on transport triggered architecture processor}, year={2005}, volume={2}, number={}, doi={10.1109/ISSCS.2005.1511285}, pages={493-496 Vol. 2},}
- @INPROCEEDINGS{289981, author={H. {Corporaal}}, booktitle={Proceedings of 4th Great Lakes Symposium on VLSI}, title={Design of transport triggered architectures}, year={1994}, doi={10.1109/GLSV.1994.289981}, volume={}, number={}, pages={130-135},}
- @INPROCEEDINGS{6128530, author={J. {Hu} and W. {Guo} and J. {Wei} and Y. {Chang} and D. {Sun}}, booktitle={2011 Fourth International Symposium on Parallel Architectures, Algorithms and Programming}, title={A Novel Architecture for Fast RSA Key Generation Based on RNS}, year={2011}, volume={}, number={}, pages={345-349}, doi={10.1109/PAAP.2011.75}}
- @INPROCEEDINGS{840031, author={V. A. {Zivkovic} and R. J. W. T. {Tangelder} and H. G. {Kerkhoff}}, booktitle={Proceedings Design, Automation and Test in Europe Conference and Exhibition 2000 (Cat. No. PR00537)}, title={Design and test space exploration of transport-triggered architectures}, year={2000}, volume={}, number={}, pages={146-151}, doi={10.1109/DATE.2000.840031}}
- @INPROCEEDINGS{1540373, author={A. {Burian} and P. {Salmela} and J. {Takala}}, booktitle={2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05)}, title={Complex fixed-point matrix inversion using transport triggered architecture}, year={2005}, volume={}, number={}, pages={107-112}, doi={10.1109/ASAP.2005.25}}
- @INPROCEEDINGS{6403142, author={S. {Hauser} and N. {Moser} and B. {Juurlink}}, booktitle={NORCHIP 2012}, title={SynZEN: A hybrid TTA/VLIW architecture with a distributed register file}, year={2012}, volume={}, number={}, pages={1-4}, doi={10.1109/NORCHP.2012.6403142}}
- @INPROCEEDINGS{6893206, author={J. {Helkala} and T. {Viitanen} and H. {Kultala} and P. {Jääskeläinen} and J. {Takala} and T. {Zetterman} and H. {Berg}}, booktitle={2014 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV)}, title={Variable length instruction compression on Transport Triggered Architectures}, year={2014}, volume={}, number={}, pages={149-155}, doi={10.1109/SAMOS.2014.6893206}}
- @INPROCEEDINGS{beldianu_ziavras_2014,
- title={ASIC Design of Shared Vector Accelerators for Multicore Processors},
- DOI={10.1109/sbac-pad.2014.13},
- journal={2014 IEEE 26th International Symposium on Computer Architecture and High Performance Computing},
- author={Beldianu, Spiridon F. and Ziavras, Sotirios G.},
- year={2014}
- },
- @INPROCEEDINGS{7530376,
- title={Encrypted computation on a one instruction set architecture},
- DOI={10.1109/iccpct.2016.7530376},
- journal={2016 International Conference on Circuit, Power and Computing Technologies (ICCPCT)},
- author={Dharshana, K. S. and Balasubramanian, Kannan and Arun, M.},
- year={2016}
- },
- @INPROCEEDINGS{5735103,
- title={Implementation of (15, 9) Reed Solomon Minimal Instruction Set Computing on FPGA using Handel-C},
- DOI={10.1109/iccaie.2010.5735103},
- journal={2010 International Conference on Computer Applications and Industrial Electronics},
- author={Ong, Jia Jan and Ang, L.-M. and Seng, K. P.},
- year={2010}
- },
- @INPROCEEDINGS{yokota_saso_hara-azumi_2017,
- title={One-instruction set computer-based multicore processors for energy-efficient streaming data processing},
- DOI={10.1145/3130265.3130318},
- journal={Proceedings of the 28th International Symposium on Rapid System Prototyping Shortening the Path from Specification to Prototype - RSP '17},
- author={Yokota, Minato and Saso, Kaoru and Hara-Azumi, Yuko},
- year={2017}
- }
- @INPROCEEDINGS{ahmed_sakamoto_anderson_hara-azumi_2015,
- title={Synthesizable-from-C Embedded Processor Based on MIPS-ISA and OISC},
- DOI={10.1109/euc.2015.23},
- journal={2015 IEEE 13th International Conference on Embedded and Ubiquitous Computing},
- author={Ahmed, Tanvir and Sakamoto, Noriaki and Anderson, Jason and Hara-Azumi, Yuko},
- year={2015}
- },
- @INPROCEEDINGS{blem_menon_sankaralingam_2013,
- title={Power struggles: Revisiting the RISC vs. CISC debate on contemporary ARM and x86 architectures},
- DOI={10.1109/hpca.2013.6522302},
- journal={2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA)},
- author={Blem, E. and Menon, J. and Sankaralingam, K.},
- year={2013}
- },
- @book{gilreath_laplante_2003,
- place={Boston},
- title={Computer Architecture: A Minimalist Perspective},
- publisher={Kluwer Academic Publishers},
- author={Gilreath, William F and Laplante, Phillip A},
- year={2003}
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- @book{harris_harris_2013,
- place={Amsterdam},
- edition={2},
- title={Digital design and computer architecture},
- publisher={Elsevier},
- author={Harris, David Money and Harris, Sarah L},
- year={2013}
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- @INPROCEEDINGS{jamil_1995,
- title={RISC versus CISC},
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- @INPROCEEDINGS{5735100,
- title={Minimal Instruction Set FPGA AES processor using Handel},
- DOI={10.1109/iccaie.2010.5735100},
- journal={2010 International Conference on Computer Applications and Industrial Electronics},
- author={Kong, J. H. and Ang, L.-M. and Seng, K. P. and Adejo, Achonu Oluwole},
- year={2010}
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- title={Atkin's Test: News from the Front},
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- @INPROCEEDINGS{5348869, author={H. {Corporaal} and H. {Mulder}}, booktitle={Supercomputing '91:Proceedings of the 1991 ACM/IEEE Conference on Supercomputing}, title={MOVE: a framework for high-performance processor design}, year={1991}, volume={}, number={}, pages={692-701}, abstract={}, keywords={Process design}, doi={10.1145/125826.126159}, ISSN={}, month={Nov},}
- @TECHREPORT{Corporaal94move32int,
- author = {Henk Corporaal},
- title = {MOVE32INT: Architecture and Programmer's Reference Manual},
- institution = {},
- year = {1994}
- }
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