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Albero (Tree):
52ff281a76
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ucl_project_y3
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simulation
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modelsim
Min
49689e242c
Do not simulate rst signal
6 anni fa
..
UCL_project_y3_run_msim_rtl_verilog.do
49689e242c
Do not simulate rst signal
6 anni fa
modelsim.ini
de18826119
Added simulation directory
6 anni fa
risc8_tb_wave.do
12417f0cb5
Working processor
6 anni fa
risc_tb_wave.do
9d5c8e7121
Project restructure
6 anni fa
top_compile.do
b346abb6a3
Big project update
6 anni fa
top_wave.do
b346abb6a3
Big project update
6 anni fa
wave.do
de18826119
Added simulation directory
6 anni fa