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  3. \contentsline {section}{\numberline {1}Abstract}{2}{section.1}% 
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  5. \contentsline {section}{\numberline {2}Introduction}{2}{section.2}% 
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  7. \contentsline {subsection}{\numberline {2.1}Aims and Objectives}{2}{subsection.2.1}% 
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  11. \contentsline {subsection}{\numberline {2.3}Project contents}{3}{subsection.2.3}% 
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  13. \contentsline {section}{\numberline {3}Goals and Objectives}{3}{section.3}% 
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  15. \contentsline {subsection}{\numberline {3.1}RISC Processor}{4}{subsection.3.1}% 
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  19. \contentsline {subsection}{\numberline {3.3}Design Criteria}{4}{subsection.3.3}% 
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  23. \contentsline {section}{\numberline {4}Theory and Analytical Bases}{4}{section.4}% 
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  25. \contentsline {subsection}{\numberline {4.1}RISC Processor}{4}{subsection.4.1}% 
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  27. \contentsline {subsubsection}{\numberline {4.1.1}Pipelining}{4}{subsubsection.4.1.1}% 
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  29. \contentsline {subsubsection}{\numberline {4.1.2}Multiple cores}{5}{subsubsection.4.1.2}% 
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  31. \contentsline {subsection}{\numberline {4.2}OISC Processor}{5}{subsection.4.2}% 
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  33. \contentsline {subsubsection}{\numberline {4.2.1}OISC Pipelining}{6}{subsubsection.4.2.1}% 
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  35. \contentsline {subsection}{\numberline {4.3}Predictions}{6}{subsection.4.3}% 
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  37. \contentsline {subsubsection}{\numberline {4.3.1}Execution time}{6}{subsubsection.4.3.1}% 
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  39. \contentsline {subsubsection}{\numberline {4.3.2}Instruction Space}{7}{subsubsection.4.3.2}% 
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  41. \contentsline {subsubsection}{\numberline {4.3.3}Resources}{7}{subsubsection.4.3.3}% 
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  43. \contentsline {section}{\numberline {5}Technical Method}{7}{section.5}% 
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  45. \contentsline {subsection}{\numberline {5.1}Machine Code}{7}{subsection.5.1}% 
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  51. \contentsline {subsection}{\numberline {5.2}Data flow}{9}{subsection.5.2}% 
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  53. \contentsline {subsubsection}{\numberline {5.2.1}RISC Datapath}{9}{subsubsection.5.2.1}% 
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  57. \contentsline {subsubsection}{\numberline {5.2.3}OISC Datapath Implementation Problems}{10}{subsubsection.5.2.3}% 
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  59. \contentsline {subsection}{\numberline {5.3}Stack}{10}{subsection.5.3}% 
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  65. \contentsline {subsection}{\numberline {5.4}Program Counters}{11}{subsection.5.4}% 
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  71. \contentsline {subsection}{\numberline {5.5}Arithmetic Logic Unit}{13}{subsection.5.5}% 
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  91. \contentsline {subsection}{\numberline {5.9}System setup}{18}{subsection.5.9}% 
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  93. \contentsline {section}{\numberline {6}Results and Analysis}{19}{section.6}% 
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  95. \contentsline {subsection}{\numberline {6.1}FPGA logic component composition}{19}{subsection.6.1}% 
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  97. \contentsline {subsection}{\numberline {6.2}Power analysis}{20}{subsection.6.2}% 
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  99. \contentsline {subsubsection}{\numberline {6.2.1}Activity Factor}{21}{subsubsection.6.2.1}% 
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  109. \contentsline {subsection}{\numberline {6.4}Maximum clock frequency}{25}{subsection.6.4}% 
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  111. \contentsline {subsection}{\numberline {6.5}Future work}{25}{subsection.6.5}% 
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  113. \contentsline {section}{\numberline {7}Conclusion}{26}{section.7}% 
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  115. \contentsline {section}{\numberline {8}Appendix}{29}{section.8}% 
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  117. \contentsline {subsection}{\numberline {8.1}Processor instruction set tables}{29}{subsection.8.1}% 
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