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index.toc 5.8 KB
Cronologia Originale

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  3. \contentsline {section}{\numberline {1}Introduction}{2}{section.1}% 
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  5. \contentsline {subsection}{\numberline {1.1}Aims and Objectives}{2}{subsection.1.1}% 
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  7. \contentsline {subsection}{\numberline {1.2}Supporting Theory}{2}{subsection.1.2}% 
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  9. \contentsline {subsection}{\numberline {1.3}Project contents}{3}{subsection.1.3}% 
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  11. \contentsline {section}{\numberline {2}Goals and Objectives}{4}{section.2}% 
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  13. \contentsline {subsection}{\numberline {2.1}RISC Processor}{4}{subsection.2.1}% 
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  15. \contentsline {subsection}{\numberline {2.2}OISC Processor}{4}{subsection.2.2}% 
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  17. \contentsline {subsection}{\numberline {2.3}Design Criteria}{4}{subsection.2.3}% 
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  19. \contentsline {subsection}{\numberline {2.4}Benchmark}{4}{subsection.2.4}% 
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  21. \contentsline {section}{\numberline {3}Theory and Analytical Bases}{4}{section.3}% 
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  23. \contentsline {subsection}{\numberline {3.1}RISC Processor}{4}{subsection.3.1}% 
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  25. \contentsline {subsubsection}{\numberline {3.1.1}Pipelining}{5}{subsubsection.3.1.1}% 
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  27. \contentsline {subsubsection}{\numberline {3.1.2}Multiple cores}{6}{subsubsection.3.1.2}% 
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  29. \contentsline {subsection}{\numberline {3.2}OISC Processor}{6}{subsection.3.2}% 
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  31. \contentsline {subsection}{\numberline {3.3}Predictions}{6}{subsection.3.3}% 
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  33. \contentsline {section}{\numberline {4}Technical Method}{7}{section.4}% 
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  35. \contentsline {subsection}{\numberline {4.1}Machine Code}{7}{subsection.4.1}% 
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  37. \contentsline {subsubsection}{\numberline {4.1.1}RISC}{7}{subsubsection.4.1.1}% 
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  39. \contentsline {subsubsection}{\numberline {4.1.2}OISC}{7}{subsubsection.4.1.2}% 
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  41. \contentsline {subsection}{\numberline {4.2}Data flow}{8}{subsection.4.2}% 
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  43. \contentsline {subsubsection}{\numberline {4.2.1}RISC Datapath}{8}{subsubsection.4.2.1}% 
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  45. \contentsline {subsubsection}{\numberline {4.2.2}OISC Datapath}{9}{subsubsection.4.2.2}% 
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  47. \contentsline {subsection}{\numberline {4.3}Stack}{9}{subsection.4.3}% 
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  49. \contentsline {subsubsection}{\numberline {4.3.1}RISC Stack}{9}{subsubsection.4.3.1}% 
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  51. \contentsline {subsubsection}{\numberline {4.3.2}OISC Stack}{9}{subsubsection.4.3.2}% 
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  53. \contentsline {subsection}{\numberline {4.4}Program Counter}{9}{subsection.4.4}% 
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  55. \contentsline {subsubsection}{\numberline {4.4.1}RISC PC}{9}{subsubsection.4.4.1}% 
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  59. \contentsline {subsection}{\numberline {4.5}Arithmetic Logic Unit}{9}{subsection.4.5}% 
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  61. \contentsline {subsubsection}{\numberline {4.5.1}OISC ALU}{10}{subsubsection.4.5.1}% 
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  65. \contentsline {subsection}{\numberline {4.6}Program Memory}{11}{subsection.4.6}% 
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  71. \contentsline {subsection}{\numberline {4.7}Instruction decoding}{12}{subsection.4.7}% 
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  73. \contentsline {subsubsection}{\numberline {4.7.1}RISC}{12}{subsubsection.4.7.1}% 
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  77. \contentsline {subsection}{\numberline {4.8}Assembly}{13}{subsection.4.8}% 
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  79. \contentsline {subsection}{\numberline {4.9}System setup}{15}{subsection.4.9}% 
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  81. \contentsline {section}{\numberline {5}Results and Analysis}{16}{section.5}% 
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  83. \contentsline {subsection}{\numberline {5.1}FPGA logic component composition}{16}{subsection.5.1}% 
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  87. \contentsline {subsubsection}{\numberline {5.2.1}Performance}{17}{subsubsection.5.2.1}% 
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  91. \contentsline {subsubsection}{\numberline {5.2.3}Program space}{18}{subsubsection.5.2.3}% 
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  93. \contentsline {subsection}{\numberline {5.3}Maximum clock frequency}{19}{subsection.5.3}% 
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  95. \contentsline {section}{\numberline {6}Conclusion}{19}{section.6}% 
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  97. \contentsline {section}{\numberline {7}Appendix}{22}{section.7}% 
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  99. \contentsline {subsection}{\numberline {7.1}Processor instruction set tables}{22}{subsection.7.1}% 
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