ucl_project_y3/docs/interim/bibliography.bib

@article{beldianu_ziavras_2014,
title={ASIC Design of Shared Vector Accelerators for Multicore Processors},
DOI={10.1109/sbac-pad.2014.13},
journal={2014 IEEE 26th International Symposium on Computer Architecture and High Performance Computing},
author={Beldianu, Spiridon F. and Ziavras, Sotirios G.},
year={2014}
},

@article{dharshana_balasubramanian_arun_2016,
title={Encrypted computation on a one instruction set architecture},
DOI={10.1109/iccpct.2016.7530376},
journal={2016 International Conference on Circuit, Power and Computing Technologies (ICCPCT)},
author={Dharshana, K. S. and Balasubramanian, Kannan and Arun, M.},
year={2016}
},

@article{ong_ang_seng_2010,
title={Implementation of (15, 9) Reed Solomon Minimal Instruction Set Computing on FPGA using Handel-C},
DOI={10.1109/iccaie.2010.5735103},
journal={2010 International Conference on Computer Applications and Industrial Electronics},
author={Ong, Jia Jan and Ang, L.-M. and Seng, K. P.},
year={2010}
},

@article{yokota_saso_hara-azumi_2017,
title={One-instruction set computer-based multicore processors for energy-efficient streaming data processing},
DOI={10.1145/3130265.3130318},
journal={Proceedings of the 28th International Symposium on Rapid System Prototyping Shortening the Path from Specification to Prototype - RSP '17},
author={Yokota, Minato and Saso, Kaoru and Hara-Azumi, Yuko},
year={2017}
}