ucl_project_y3/docs/final_report/3-objectives.tex

% !TeX root = index.tex
\iffalse
This chapter describes your Goals and Objectives. 
Indicate how your work is intended to expand on previous historical work.
Present your motivations; why are you doing this?
Indicate the type of project you have(see the list above).

Types of Projects:
2) Design and Construction projects:
These types of projects involve the design and construction of some 
electrical or electronic apparatus or device within the bounds 
of the department's educational mandate.
\fi


This project can be classified as Design and Construction which explores alternative designs of processor architecture and microarchitecture. :
\begin{enumerate}
	\item Study and explore computer architectures, SystemVerilog and assembly languages. 
	\item Compare how well OISC \texttt{MOVE} architecture would perform in low performance microcontroller application comparing to equivalent and most commonly used RISC architecture.
	\item View an alternative method of using OISC \texttt{MOVE} in a SISO (single instruction, single operation) structure, comparing to more commonly implemented TTAs VLIW architectures that are either SIMO or SIMT structure.
\end{enumerate}


\subsection{RISC Processor}
As this is aimed for low power and performance applications it will be 8bit word processor with four general purpose registers, structure is similar to MIPS.
RISC architecture will be mainly based on MIPS architecture explained in \autocite{harris_harris_2013}, except it this RISC processor would have 8bit databus and would have multiple optimisations related to 8bit limits. Some minimalistic ideas was also from \autocite{gilreath_laplante_2003}.


\subsection{OISC Processor}
There are number of different implementations that uses only single instruction. OISC \texttt{MOVE} has many benefits from VLIW and SIMO or SIMT design, however there is a lack of research investigating and comparing more general purpose OISC \texttt{MOVE} 8bit processor with short instruction word and SISO configuration.  The main theory for building OISC architecture will be based on \autocite{gilreath_laplante_2003}.

\subsection{Design Criteria}
In order for fair comparison between both architectures, a common design criteria:
\begin{description}
	\item[$\bullet$] Minimal instruction size
	\item[$\bullet$] Minimalistic design
	\item[$\bullet$] 8bit data bus width
	\item[$\bullet$] 16bit ROM address width
	\item[$\bullet$] 24bit RAM address width
	\item[$\bullet$] 16bit RAM word size
\end{description}
When constructing these points, time and equipment resources were taken into consideration. 

\subsection{Benchmark}
This benchmark include different algorithms that are commonly used in 8bit microcontrollers, IoT devices or similar low power microprocessor applications.


\iffalse
This is just a list of research papers and relative context:
\autocite{5936440} - Novel processor for Multiple Instruction Multiple Data packet triggered architecture for pipeline and parallel processing.


\autocite{7363689} - Implementing TTA for SDR and focuses on power optimisations. It show ~24.8-26.1\% decrease in power consumption with 3.3\% area increase.
\autocite{1511285} - Scalable FIR filtering on TTA
\autocite{289981} - MOVE32INT TTA implementation. Achieved parallel processing with 80MHz 320Mops/s comparing to RISC 20MHz 20Mops/s. Includes automated design
\autocite{6855236} - Parallel programming of a TTA for LDPC encoding application
\autocite{922340} - TTA for encryption specific ASIP
\autocite{8682289} - Low power implementation TTA for FFT
\autocite{6128530} - Implemented TTA that is efficent on RSA calculations, 3 1024bit pairs/s at 100MHz
\autocite{1540373} - ASIP TTA for matrix inversion.
\autocite{6403142} - A novel microachitecture that combines VLIW and TTA for different applications. Takes less area than existing TTA and VLIW
\autocite{8573494} - Compressive Sensing Applications on ARM Cortex-A15, NIOS II and TTA architectures. TTA has lowest time and power consumption, however about 2.5 higher area to NIOS II

\autocite{840031}  - Introduce Test space exploration costs for TTA templates.


\autocite{4595596} - Focuses on software pipelining and solved with GNU Linear Programming Kit (Very interesting)
\autocite{8425389} - Using soft cores in comparision to VLIW to have 67\% of resources with up to 88\% improvement in execution time and 21-49\% cost in program size.


\autocite{5403730} - TTA instruction redundancy remoal method with base plus offset addressing load/store function unit (LSFU)
\autocite{6972455} - Reducing VLIW interconnects to achieve 10\% core energy in 4-issue VLIW
\autocite{1207041} - Try to reduce power by encoding buses thus reducing switching (read a bit more)
\autocite{4627144} - TTA code compression using arithmetic coding
\autocite{1213033} - Another template based compression method to improve code density
\autocite{6893206} - Instruction template based compression method for TTA processors
\fi