\iffalse
This chapter describes your Goals and Objectives. 
Indicate how your work is intended to expand on previous historical work.
Present your motivations; why are you doing this?
Indicate the type of project you have(see the list above).

Types of Projects:
2) Design and Construction projects:
These types of projects involve the design and construction of some 
electrical or electronic apparatus or device within the bounds 
of the department's educational mandate.
\fi


This is just a list of research papers and relative context:


\autocite{5403730} - TTA instruction redundancy remoal method with base plus offset addressing load/store function unit (LSFU)
\autocite{4627144} - TTA code compression using arithmetic coding
\autocite{5936440} - Novel processor for Multiple Instruction Multiple Data packet triggered architecture for pipeline and parallel processing.
\autocite{1213033} - Another template based compression method to improve code density


\autocite{1511285} - Scalable FIR filtering on TTA
\autocite{289981} - MOVE32INT TTA implementation. Achieved parallel processing with 80MHz 320Mops/s comparing to RISC 20MHz 20Mops/s. Includes automated design
\autocite{6855236} - Parallel programming of a TTA for LDPC encoding application
\autocite{922340} - TTA for encryption specific ASIP
\autocite{4595596} - Focuses on software pipelining and solved with GNU Linear Programming Kit (Very interesting)
\autocite{1207041} - Try to reduce power by encoding buses thus reducing switching (read a bit more)
\autocite{6972455} - Reducing VLIW interconnects to achieve 10\% core energy in 4-issue VLIW
\autocite{7363689} - Implementing TTA for SDR and focuses on power optimisations. It show ~24.8-26.1\% decrease in power consumption with 3.3\% area increase.
\autocite{8425389} - Using soft cores in comparision to VLIW to have 67\% of resources with up to 88\% improvement in execution time and 21-49\% cost in program size.
\autocite{8682289} - Low power implementation TTA for FFT
\autocite{8573494} - Compressive Sensing Applications on ARM Cortex-A15, NIOS II and TTA architectures. TTA has lowest time and power consumption, however about 2.5 higher area to NIOS II

\autocite{6128530} - Implemented TTA that is efficent on RSA calculations, 3 1024bit pairs/s at 100MHz
\autocite{1540373} - ASIP TTA for matrix inversion.
\autocite{840031}  - Introduce Test space exploration costs for TTA templates.
\autocite{6403142} - A novel microachitecture that combines VLIW and TTA for different applications. Takes less area than existing TTA and VLIW
\autocite{6893206} - Instruction template based compression method for TTA processors

