Wokring OISC prototype

Working OISC in modelsim. Many fixed have been done to make it
synthesisable by quartus.

src/oisc/cpu.sv

@@ -5,31 +5,29 @@ import oisc8_pkg::*;
 
 module oisc8_cpu(processor_port port);
 	
-	wire [`DWIDTH-1:0] data_bus;
-	wire [`DAWIDTH+`SAWIDTH:0] instr_bus;  
-	
-	IBus bus0(
-			.clk(port.clk),
-			.rst(port.rst),
-			.instr(instr_bus),
-			.data(data_bus)
-	);
-	
+	wire[`SAWIDTH+`DAWIDTH:0] instr0;
+	IBus bus0(port.clk, port.rst, instr0);
+	//assign bus.clk = port.clk;
+	//assign bus.rst = port.rst;
+	//oconn oc(port, bus0.host);	
 	// NULL block always return 0 and ignores input.
 	//Port #() p_null0(
 	//		.bus(bus0),
 	//		.data_to_bus(8'd0)
 	//);
 	//Port #(.ADDR)
-	PortOutput#() p_null(.bus(bus0),.data_to_bus(`DWIDTH'd0));
-	pc_block#(.PROGRAM("../../memory/oisc8.text")) pc0(bus0);
-	alu_block alu0(bus0);
-	mem_block ram0(bus0, port);
-	oisc_com_block com0(bus0, port);
+	PortOutput p_null(.bus(bus0.port),.data_to_bus(`DWIDTH'd0));
+	pc_block#(.PROGRAM("../../memory/oisc8.text")) pc0(bus0.port, instr0);
+	alu_block alu0(bus0.port);
+	mem_block ram0(bus0.port, port);
+	oisc_com_block com0(bus0.port, port);
 
 endmodule
 
-module pc_block(IBus bus);
+module pc_block(
+		IBus.port bus, 
+		output wire[`SAWIDTH+`DAWIDTH:0] instr
+	);
 
 	parameter PROGRAM = "";
 	reg[15:0] pc, pcn, pcr; // Program counter
@@ -54,7 +52,7 @@ module pc_block(IBus bus);
 	 		.NUMWORDS(2048)
 	) 
 	`endif
-		rom0(pc[12:0], bus.clk, bus.instr[12:0]);
+		rom0(pc[12:0], bus.clk, instr[12:0]);
 	
 	`ifndef SYNTHESIS
 	reg [15:0] pcp;  // Current program counter for debugging
@@ -88,7 +86,7 @@ module pc_block(IBus bus);
 
 endmodule
 
-module oisc_com_block(IBus bus, processor_port port);
+module oisc_com_block(IBus.port bus, processor_port port);
 	reg [7:0] addr;
 	reg wr,rd;
 	assign port.com_addr = wr|rd ? addr : 8'd0;
@@ -103,7 +101,7 @@ module oisc_com_block(IBus bus, processor_port port);
 	);
 endmodule
 
-module mem_block(IBus bus, processor_port port);
+module mem_block(IBus.port bus, processor_port port);
 	reg w0,w1,w2,wd0,wd1;
 	reg [15:0] data, cached;
 	reg [23:0] pointer;
@@ -193,7 +191,7 @@ module mem_block(IBus bus, processor_port port);
 	//end
 endmodule
 
-module alu_block(IBus bus);
+module alu_block(IBus.port bus);
 	logic [`DWIDTH-1:0] acc0, acc1;	
 	
 	PortReg#(.ADDR_SRC(ALUACC0R), .ADDR_DST(ALUACC0)) p_aluacc0(

src/oisc/oisc.sv

@@ -5,75 +5,81 @@
 package oisc8_pkg;
 
 	typedef enum logic [`DAWIDTH-1:0] {
-		ALUACC0 ='d0,
-		ALUACC1 ='d1,
-		BRPT0   ='d2,
-		BRPT1   ='d3,
-		BRZ     ='d4,
-		STACK   ='d5,
-		MEMPT0  ='d6,
-		MEMPT1  ='d7,
-		MEMPT2  ='d8,
-		MEMSWHI ='d9,
-		MEMSWLO ='d10,
-		COMA    ='d11,
-		COMD    ='d12
+		ALUACC0 =`DAWIDTH'd0,
+		ALUACC1 =`DAWIDTH'd1,
+		BRPT0   =`DAWIDTH'd2,
+		BRPT1   =`DAWIDTH'd3,
+		BRZ     =`DAWIDTH'd4,
+		STACK   =`DAWIDTH'd5,
+		MEMPT0  =`DAWIDTH'd6,
+		MEMPT1  =`DAWIDTH'd7,
+		MEMPT2  =`DAWIDTH'd8,
+		MEMSWHI =`DAWIDTH'd9,
+		MEMSWLO =`DAWIDTH'd10,
+		COMA    =`DAWIDTH'd11,
+		COMD    =`DAWIDTH'd12
 	} e_iaddr_dst;  // destination enum
 
 	typedef enum logic [`SAWIDTH-1:0] {
-		NULL    ='d0,
+		NULL    =`SAWIDTH'd0,
 		// ALU BLOCK
-		ALUACC0R='d1,
-		ALUACC1R='d2,
-		ADD     ='d3,
-		ADDC    ='d4,
-		SUB     ='d5,
-		SUBC    ='d6,
-		AND     ='d7,
-		OR      ='d8,
-		XOR     ='d9,	
-		SLL     ='d11,	
-		SRL     ='d12,	
-		EQ     	='d13,	
-		GT     	='d14,	
-		GE    	='d15,	
-		MULLO   ='d16,	
-		MULHI   ='d17,	
-		DIV     ='d18,	
-		MOD     ='d19,
+		ALUACC0R=`SAWIDTH'd1,
+		ALUACC1R=`SAWIDTH'd2,
+		ADD     =`SAWIDTH'd3,
+		ADDC    =`SAWIDTH'd4,
+		SUB     =`SAWIDTH'd5,
+		SUBC    =`SAWIDTH'd6,
+		AND     =`SAWIDTH'd7,
+		OR      =`SAWIDTH'd8,
+		XOR     =`SAWIDTH'd9,	
+		SLL     =`SAWIDTH'd11,	
+		SRL     =`SAWIDTH'd12,	
+		EQ     	=`SAWIDTH'd13,	
+		GT     	=`SAWIDTH'd14,	
+		GE    	=`SAWIDTH'd15,	
+		MULLO   =`SAWIDTH'd16,	
+		MULHI   =`SAWIDTH'd17,	
+		DIV     =`SAWIDTH'd18,	
+		MOD     =`SAWIDTH'd19,
 		// Program Counter
-		BRPT0R  ='d20,
-		BRPT1R  ='d21,
+		BRPT0R  =`SAWIDTH'd20,
+		BRPT1R  =`SAWIDTH'd21,
 		// Memory
-		MEMPT0R ='d22,
-		MEMPT1R ='d23,
-		MEMPT2R ='d24,
-		MEMLWHI ='d25,
-		MEMLWLO ='d26,
-		STACKR	='d27,
-		STPT0R  ='d28,
-		STPT1R  ='d29,
+		MEMPT0R =`SAWIDTH'd22,
+		MEMPT1R =`SAWIDTH'd23,
+		MEMPT2R =`SAWIDTH'd24,
+		MEMLWHI =`SAWIDTH'd25,
+		MEMLWLO =`SAWIDTH'd26,
+		STACKR	=`SAWIDTH'd27,
+		STPT0R  =`SAWIDTH'd28,
+		STPT1R  =`SAWIDTH'd29,
 		// COM
-		COMAR   ='d30,
-		COMDR   ='d31		
+		COMAR   =`SAWIDTH'd30,
+		COMDR   =`SAWIDTH'd31		
 	} e_iaddr_src;  // source enum
 
 endpackage
 
-interface IBus(clk, rst, data, instr);
+interface IBus(clk, rst, instr);
 	import oisc8_pkg::*;
 	
-	input logic clk, rst;
-	inout wire[`DWIDTH-1:0] data;
+	input wire clk, rst;	
 	input wire[`SAWIDTH+`DAWIDTH:0] instr;
 
+	wire[`DWIDTH-1:0] data;
+
 	logic imm;
 	e_iaddr_dst instr_dst;
 	e_iaddr_src instr_src;
 	assign imm = instr[`DAWIDTH+`SAWIDTH];
 	assign instr_dst = e_iaddr_dst'(instr[`DAWIDTH+`SAWIDTH-1:`SAWIDTH]);
 	assign instr_src = e_iaddr_src'(instr[`SAWIDTH-1:0]);
-
+	
+	modport port(
+		input clk, rst, imm, instr_dst, instr_src,
+		inout data
+	);
+	//modport host(output clk, rst);
 endinterface
 
 module PortReg(bus, data_from_bus, data_to_bus, rd, wr);
@@ -89,15 +95,24 @@ module PortReg(bus, data_from_bus, data_to_bus, rd, wr);
 	parameter DEFAULT = `DWIDTH'd0;
 
 	reg [`SAWIDTH-1:0] data;
-	always_comb casez({bus.imm,bus.rst})
-		2'b00: data = bus.data[`SAWIDTH-1:0];
-		2'b10: data = bus.instr_src;
-		2'b?1: data = DEFAULT;
-	endcase
-
-	assign wr = bus.instr_dst == ADDR_DST;
-	assign rd = bus.instr_src == ADDR_SRC;
-	assign bus.data = rd ? data_to_bus : 'bZ;
+	always_comb begin
+		 casez({bus.imm,bus.rst})
+			2'b00: data = bus.data[`SAWIDTH-1:0];
+			2'b10: data = bus.instr_src;
+			2'b?1: data = DEFAULT;
+		endcase
+
+		wr = (bus.instr_dst == ADDR_DST);
+		rd = (bus.instr_src == ADDR_SRC);
+	end
+	
+	genvar i;
+	generate 
+		for(i=0;i<`DWIDTH;i=i+1) begin : generate_data_buf
+			bufif1(bus.data[i], data_to_bus[i], rd);
+		end 
+	endgenerate
+
 	always_ff@(posedge bus.clk) begin
 		if(bus.rst) data_from_bus <= DEFAULT;
 		else if(wr) data_from_bus <= data;
@@ -117,20 +132,31 @@ module PortRegSeq(bus, data_from_bus, data_to_bus, rd, wr);
 	parameter DEFAULT = `DWIDTH'd0;
 
 	reg [`SAWIDTH-1:0] data, latch;
-	always_comb casez({bus.imm,bus.rst})
-		2'b00: data = bus.data[`SAWIDTH-1:0];
-		2'b10: data = bus.instr_src;
-		2'b?1: data = DEFAULT;
-	endcase
-
-	assign wr = bus.instr_dst == ADDR_DST;
-	assign rd = bus.instr_src == ADDR_SRC;
-	assign bus.data = rd ? data_to_bus : 'bZ;
-	assign data_from_bus = wr ? data : latch;
+	always_comb begin 
+		casez({bus.imm,bus.rst})
+			2'b00: data = bus.data[`SAWIDTH-1:0];
+			2'b10: data = bus.instr_src;
+			2'b?1: data = DEFAULT;
+		endcase
+
+		wr = (bus.instr_dst == ADDR_DST);
+		rd = (bus.instr_src == ADDR_SRC);
+		data_from_bus = wr ? data : latch;
+
+	end
+
 	always_ff@(posedge bus.clk) begin
 		if(bus.rst) latch <= DEFAULT;
 		else if(wr) latch <= data;
 	end
+
+	genvar i;
+	generate 
+		for(i=0;i<`DWIDTH;i=i+1) begin : generate_data_buf
+			bufif1(bus.data[i], data_to_bus[i], rd);
+		end 
+	endgenerate
+
 endmodule
 
 module PortInput(bus, data_from_bus, wr, rst);
@@ -145,9 +171,12 @@ module PortInput(bus, data_from_bus, wr, rst);
 	parameter DEFAULT = `DWIDTH'd0;
 
 	reg [`SAWIDTH-1:0] data;
-	assign data = bus.imm ? bus.instr_src : bus.data[`SAWIDTH-1:0];
 
-	assign wr = bus.instr_dst == ADDR;
+	always_comb begin
+		data = bus.imm ? bus.instr_src : bus.data[`SAWIDTH-1:0];
+		wr = (bus.instr_dst == ADDR);
+	end
+
 	always_ff@(posedge bus.clk) begin
 		if(bus.rst|rst) 
 			data_from_bus <= DEFAULT;
@@ -167,9 +196,11 @@ module PortInputSeq(bus, data_from_bus, wr);
 	parameter DEFAULT = `DWIDTH'd0;
 
 	reg [`SAWIDTH-1:0] data;
-	assign data = bus.imm ? bus.instr_src : bus.data[`SAWIDTH-1:0];
-	assign wr = bus.instr_dst == ADDR;
-	assign data_from_bus = wr ? data : DEFAULT;
+	always_comb begin
+		data = bus.imm ? bus.instr_src : bus.data[`SAWIDTH-1:0];
+		wr = (bus.instr_dst == ADDR);
+		data_from_bus = wr ? data : DEFAULT;
+	end
 endmodule
 
 
@@ -180,8 +211,16 @@ module PortOutput(bus, data_to_bus, rd);
 	input  reg[`SAWIDTH-1:0] data_to_bus;
 	output reg rd;
 
-	parameter ADDR = e_iaddr_src'(0);
+	//parameter ADDR = e_iaddr_src'(`SAWIDTH'd0);
+	parameter ADDR = `SAWIDTH'd0;
+
+	always_comb rd = (bus.instr_src == ADDR);
+
+	genvar i;
+	generate 
+		for(i=0;i<`DWIDTH;i=i+1) begin : generate_data_buf
+			bufif1(bus.data[i], data_to_bus[i], rd);
+		end 
+	endgenerate
 
-	assign rd = bus.instr_src == ADDR;
-	assign bus.data = rd ? data_to_bus : 'bZ;
 endmodule

tools/oisc8asm.py

@@ -90,7 +90,7 @@ class InstructionDest:
         if len(operands) != 1:
             raise CompilingError(f"Instruction has invalid amount of operands")
 
-        if operands[0] in instrSrc:
+        if operands[0].upper() in instrSrc:
             src = instrSrc[operands[0]]
             immediate = 0
         else: