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@@ -25,6 +25,7 @@ module oisc8_cpu(processor_port port);
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pc_block#(.PROGRAM("../../memory/oisc8.text")) pc0(bus0);
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pc_block#(.PROGRAM("../../memory/oisc8.text")) pc0(bus0);
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alu_block alu0(bus0);
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alu_block alu0(bus0);
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mem_block ram0(bus0, port);
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mem_block ram0(bus0, port);
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+ oisc_com_block com0(bus0, port);
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endmodule
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endmodule
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@@ -87,6 +88,21 @@ module pc_block(IBus bus);
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endmodule
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endmodule
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+module oisc_com_block(IBus bus, processor_port port);
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+ reg [7:0] addr;
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+ reg wr,rd;
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+ assign port.com_addr = wr|rd ? addr : 8'd0;
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+ PortReg#(.ADDR_SRC(COMAR), .ADDR_DST(COMA)) p_coma(
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+ .bus(bus),.data_from_bus(addr),.data_to_bus(addr),.wr(),.rd()
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+ );
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+ PortInputSeq#(.ADDR(COMD)) p_comd(
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+ .bus(bus),.data_from_bus(port.com_wr),.wr(wr)
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+ );
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+ PortOutput#(.ADDR(COMDR)) p_comdr(
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+ .bus(bus),.data_to_bus(port.com_rd),.rd(rd)
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+ );
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+endmodule
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+
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module mem_block(IBus bus, processor_port port);
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module mem_block(IBus bus, processor_port port);
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reg w0,w1,w2,wd0,wd1;
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reg w0,w1,w2,wd0,wd1;
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reg [15:0] data, cached;
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reg [15:0] data, cached;
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