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@@ -39,6 +39,7 @@ module top(
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`ifdef SYNTHESIS
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initial $display("Assuming this is synthesis");
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+ // Adding external reset source
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wire debug_rst;
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sys_ss#("RST") sys_ss_rst(debug_rst);
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assign rst = ~KEY[0] | debug_rst;
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@@ -81,6 +82,22 @@ module top(
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`endif
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ram_block0(ram_addr[11:0], mclk, ram_wr_data, ram_wr_en, ram_rd_en, ram_rd_data);
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+ `ifdef SYNTHESIS
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+ reg[23:0] ram_addr_rd_pr, ram_addr_wr_pr;
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+ reg[15:0] ram_data_rd_pr, ram_data_wr_pr;
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+ reg ram_rd_pr0;
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+ always_ff@(posedge mclk) begin
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+ ram_rd_pr0 <= ram_rd_en;
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+ if(ram_wr_en) begin
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+ ram_addr_wr_pr <= ram_addr;
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+ ram_data_wr_pr <= ram_wr_data;
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+ end
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+ if(ram_rd_en) ram_addr_rd_pr <= ram_addr;
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+ if(ram_rd_pr0) ram_data_rd_pr <= ram_rd_data;
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+ end
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+ sys_sp#("ramw",40) sys_ramw({ram_addr_wr_pr,ram_data_wr_pr});
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+ sys_sp#("ramr",40) sys_ramr({ram_addr_rd_pr,ram_data_rd_pr});
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+ `endif
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//sdram_block sdram0(
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// .mclk(mclk),
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// .fclk(fclk),
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