Minor fixes

Fixed some register sizes & code order. Updated UART block

src/project.sv

@@ -37,10 +37,15 @@ module com_block(
 );
 
 	/* UART */
-	reg [2:0] uart0_reg;
+	reg [3:0] uart0_reg;
+	// UART REG
+	// 0: Is Recieving
+	// 1: Is Transmitting
+	// 2: Echo ON
+	// 3: Recieved and waiting 
 	reg uart0_recv;
 	reg uart0_transmit;
-	reg [7:0] tx_byte, rx_byte;
+	reg [7:0] tx_byte, rx_byte, rx_buf;
 	// Clock divide = 1e6 / (9600 * 4)
 	//uart#(.CLOCK_DIVIDE(1302)) uart0(
 	uart#(.CLOCK_DIVIDE(26)) uart0(
@@ -77,9 +82,11 @@ module com_block(
 		if(rst) begin 
 			//reset_seq <= 0;
 			uart0_reg[2] <= 0;
+			uart0_reg[3] <= 0;
 			//interrupt <= 0;
 			interrupt_reg <= 0;
 			leds <= 'b0000_0000;
+			rx_buf <= 0;
 		end
 		//else if(~uart0_reg[2] && reset_seq != 7) reset_seq <= reset_seq + 1;
 		else begin
@@ -89,7 +96,12 @@ module com_block(
 			endcase
 			if(~key1) interrupt_reg <= 1;
 			if(interrupt) interrupt_reg <= 0;
-			leds <= {5'b0, uart0_reg};
+			leds <= {3'b0, uart0_recv, uart0_reg};
+			if(uart0_recv) begin 
+					uart0_reg[3] <= 1;
+					rx_buf <= rx_byte;
+			end
+			if(~uart0_recv & addr == 8'h09) uart0_reg[3] <= 0;
 		end
 	end
 
@@ -101,10 +113,11 @@ module com_block(
 		//tx_byte = in_data;
 		case(addr)
 			8'h03: out_data = in_data; 				// Set uart0 flags
-			8'h04: out_data = {5'b0, uart0_reg};  	// Read uart0 flags
+			8'h04: out_data = {4'b0, uart0_reg};  	// Read uart0 flags
 			8'h05: out_data = in_data;  			// Write to uart0
 			8'h07: out_data = leds;					// Read current LEDs
 			8'h08: out_data = {4'b0, switches};		// Read DIP
+			8'h09: out_data = rx_buf;  			// Write to uart0
 			default: out_data = 0;
 		endcase
 	end

src/risc/controller.csv

@@ -21,9 +21,9 @@
      CI2,   ALU_NONE,  SB_NONE,         0,  SR_NONE,      0,      0,         0,SO_MEML , ST_SKIP, PC_NONE ,IMO_2,2'b00  , INTR_NONE
     ADDC,    ALU_ADD,     SB_0,         1,  SR_ALUL,      0,      0,         0,SO_MEML , ST_SKIP, PC_NONE ,IMO_NONE,2'b01 , INTR_NONE
     SUBC,    ALU_SUB,     SB_0,         1,  SR_ALUL,      0,      0,         0,SO_MEML , ST_SKIP, PC_NONE ,IMO_NONE,2'b01 , INTR_NONE
-     SLL,     ALU_SL,   SB_REG,         1,  SR_ALUL,      0,      0,         0,SO_MEML , ST_SKIP, PC_NONE ,IMO_NONE,2'b00  , INTR_NONE
-     SRL,     ALU_SR,   SB_REG,         1,  SR_ALUL,      0,      0,         0,SO_MEML , ST_SKIP, PC_NONE ,IMO_NONE,2'b00  , INTR_NONE
-     SRA,     ALU_RA,   SB_REG,         1,  SR_ALUL,      0,      0,         0,SO_MEML , ST_SKIP, PC_NONE ,IMO_NONE,2'b00  , INTR_NONE
+     SLL,     ALU_SL,   SB_IMM,         1,  SR_ALUL,      0,      0,         1,SO_MEML , ST_SKIP, PC_NONE ,IMO_NONE,2'b00  , INTR_NONE
+     SRL,     ALU_SR,   SB_IMM,         1,  SR_ALUL,      0,      0,         1,SO_MEML , ST_SKIP, PC_NONE ,IMO_NONE,2'b00  , INTR_NONE
+     SRA,     ALU_RA,   SB_IMM,         1,  SR_ALUL,      0,      0,         1,SO_MEML , ST_SKIP, PC_NONE ,IMO_NONE,2'b00  , INTR_NONE
     LWHI,   ALU_NONE,  SB_NONE,         1,  SR_MEMH,      1,      0,         3,SO_MEML , ST_SKIP, PC_NONE ,IMO_NONE,2'b00  , INTR_NONE
     SWHI,   ALU_NONE,  SB_NONE,         0,  SR_NONE,      0,      0,         0,SO_MEMH , ST_SKIP, PC_NONE ,IMO_NONE,2'b00  , INTR_NONE
     LWLO,   ALU_NONE,  SB_NONE,         1,  SR_MEML,      1,      0,         3,SO_MEML , ST_SKIP, PC_NONE ,IMO_NONE,2'b00  , INTR_NONE

src/risc/controller.sv

@@ -422,12 +422,12 @@ module controller8(
         end
         SLL    : begin
             cdi.alu_op   = ALU_SL;
-            cdi.selb     = SB_REG;
+            cdi.selb     = SB_IMM;
             cdi.rw_en    = 1;
             cdi.selr     = SR_ALUL;
             mem_rd       = 0;
             mem_wr       = 0;
-            cdi.isize    = 0;
+            cdi.isize    = 1;
             cdi.selo     = SO_MEML;
             cdi.stackop  = ST_SKIP;
             cdi.pcop     = PC_NONE;
@@ -440,12 +440,12 @@ module controller8(
         end
         SRL    : begin
             cdi.alu_op   = ALU_SR;
-            cdi.selb     = SB_REG;
+            cdi.selb     = SB_IMM;
             cdi.rw_en    = 1;
             cdi.selr     = SR_ALUL;
             mem_rd       = 0;
             mem_wr       = 0;
-            cdi.isize    = 0;
+            cdi.isize    = 1;
             cdi.selo     = SO_MEML;
             cdi.stackop  = ST_SKIP;
             cdi.pcop     = PC_NONE;
@@ -458,12 +458,12 @@ module controller8(
         end
         SRA    : begin
             cdi.alu_op   = ALU_RA;
-            cdi.selb     = SB_REG;
+            cdi.selb     = SB_IMM;
             cdi.rw_en    = 1;
             cdi.selr     = SR_ALUL;
             mem_rd       = 0;
             mem_wr       = 0;
-            cdi.isize    = 0;
+            cdi.isize    = 1;
             cdi.selo     = SO_MEML;
             cdi.stackop  = ST_SKIP;
             cdi.pcop     = PC_NONE;

src/risc/datapath.sv

@@ -123,9 +123,14 @@ module datapath8(
 			(~cdi.isize[1]&~cdi.isize[0])|(cdi.isize[1]&~cdi.isize[0])
 		}; // Adding 1 to 2bit value.
 
-		intr_re = cdi.intr_ctl == INTR_RE;
-		pcs = intr_re | interrupt | rst;
 		
+		intr_re = cdi.intr_ctl == INTR_RE;
+		casez({intr_re, interrupt, rst})
+			3'b000: pcb = pch;
+			3'b100: pcb = intrr;
+			3'b?10: pcb = intre;
+			3'b??1: pcb = 16'h0000;
+		endcase
 		case(cdi.pcop)
 			PC_NONE: pcn0 = pcb;
 			PC_MEM : pcn0 = mem_rd;
@@ -136,12 +141,7 @@ module datapath8(
 
 		pcn = (cdi.pcop == PC_IMM | cdi.pcop == PC_IMM2) ? pcn0 : pcn0 + pc_off;
 		pca = (pchf) ? pch : pcn;
-		casez({intr_re, interrupt, rst})
-			3'b000: pcb = pch;
-			3'b100: pcb = intrr;
-			3'b?10: pcb = intre;
-			3'b??1: pcb = 16'h0000;
-		endcase
+		pcs = intr_re | interrupt | rst;
 		pc = (pcs) ? pcb : pca;
 		
 
@@ -223,23 +223,11 @@ module datapath8(
 	// 		Register File 	 	//
 	// ======================== //
 	
-	word reg_wr, reg_wr1, reg_wr2, reg_wra;
+	word reg_wr, reg_wr1, reg_wr2;
+	reg [1:0]reg_wra;
 	reg reg_wr_en1; 
 	reg [1:0]reg_wr_mem;
 	
-	always_ff@(posedge clk) begin
-		if(rst) begin
-			reg_wr1 	<= 0;
-			reg_wr_en1 	<= 0;
-			reg_wr_mem 	<= 0;
-		end else begin
-			reg_wr1 	<= reg_wr;
-			reg_wr_en1 	<= cdi.rw_en;
-			reg_wra 	<= cdi.a3;
-			reg_wr_mem 	<= {cdi.selr == SR_MEML, cdi.selr == SR_MEMH};
-		end
-	end	
-
 	always_comb begin
 		case(cdi.selr)
 			SR_REG : reg_wr = r2;
@@ -254,6 +242,19 @@ module datapath8(
 		endcase
 	end
 	
+	always_ff@(posedge clk) begin
+		if(rst) begin
+			reg_wr1 	<= 0;
+			reg_wr_en1 	<= 0;
+			reg_wr_mem 	<= 0;
+		end else begin
+			reg_wr1 	<= reg_wr;
+			reg_wr_en1 	<= cdi.rw_en;
+			reg_wra 	<= cdi.a3;
+			reg_wr_mem 	<= {cdi.selr == SR_MEML, cdi.selr == SR_MEMH};
+		end
+	end	
+
 	always_comb begin
 		case(reg_wr_mem)
 			2'b10: 		reg_wr2 = mem_rd[7:0];