Min 5 anni fa
parent
commit
c9b94ea66b
4 ha cambiato i file con 5992 aggiunte e 0 eliminazioni
  1. 4801 0
      docs/tests/cycles.eps
  2. 50 0
      docs/tests/cycles.m
  3. 1125 0
      docs/tests/power.eps
  4. 16 0
      docs/tests/power_tests.m

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docs/tests/cycles.eps


+ 50 - 0
docs/tests/cycles.m

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+close all
+data = [
+    0 963;
+    0 663;
+    0 598;
+    0 1076;
+    0 99;
+    0 49;
+    0 55];
+grid on
+legend
+B = bar(1:7,data);
+x_labels = [
+    {'\begin{tabular}{r}\texttt{Divide}\\\texttt{FFFFh/0001h}\end{tabular}'}
+    {'\begin{tabular}{r}\texttt{Divide}\\\texttt{FFFFh/FFFFh}\end{tabular}'}
+    {'\begin{tabular}{r}\texttt{Divide}\\\texttt{0001h/FFFFh}\end{tabular}'}
+    {'\begin{tabular}{r}\texttt{Modulus}\\\texttt{FFFFh\%0001h}\end{tabular}'}
+    {'\begin{tabular}{r}\texttt{Modulus}\\\texttt{FFFFh\%FFFFh}\end{tabular}'}
+    {'\begin{tabular}{r}\texttt{Modulus}\\\texttt{0001h\%FFFFh}\end{tabular}'}
+    {'\begin{tabular}{r}\texttt{Multiply 16bit}\end{tabular}'}
+];
+set(gca,'XTickLabel', x_labels, 'TickLabelInterpreter', 'latex')
+title("Power consumtion of implemented design on FPGA")
+ylabel("Numer of cycles")
+xtickangle(40);
+xtips1 = [1:7] - 0.21;
+ytips1 = B(1).YData;
+labels1 = ['N/A'];
+text(xtips1,ytips1,labels1,'HorizontalAlignment','center','VerticalAlignment','bottom');
+xtips2 = [1:7] + 0.21;
+ytips2 = B(2).YData;
+labels2 = string(B(2).YData);
+text(xtips2,ytips2,labels2,'HorizontalAlignment','center','VerticalAlignment','bottom');
+
+legend("RISC", "OISC");
+grid on
+
+
+%%
+figure
+P = [359.09 360.851 360.732];
+Pstd = [0.245 0.239 0.223];
+bar(1:3,P)                
+hold on
+er = errorbar(1:3, P, -Pstd./2,+Pstd./2); 
+er.Color = [0 0 0];
+er.LineStyle = 'none';
+set(gca,'xticklabel',{'None'; 'RISC'; 'OISC'})
+ylabel("Power (mW)")
+title("Power consumtion of implemented design on FPGA")

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docs/tests/power.eps


+ 16 - 0
docs/tests/power_tests.m

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+% matrix of [shunt volt mean, shunt volt std, supply volt, supply std]
+shunt=1.020;  %ohms
+data = [
+    80.599e-3   49e-6     4.0162  2e-3      % Empty FPGA
+    89.47e-3    36e-6     4.0243  2.214e-3  % Empty socket test
+    89.849e-3   33.1e-6   4.026   6e-3      % OISC8 mult 16bit loop
+    89.968e-3   35.6e-6   4.0222  2.47e-3   % RISC8 mult 16bit loop
+];
+
+I=data(:,1)*shunt;  % current vector
+P=(data(:,3)-data(:,1)).*I;  % power in W
+Pstd=data(:,2).*data(:,4);
+
+bar(1:4,P)                
+hold on
+er = errorbar(1:4,P,-Pstd./2,+Pstd./2);