Final report, finished content

docs/final_report/8-appendix.tex

@@ -25,7 +25,7 @@ AND  & Logical AND & 0 \\
 OR   & Logical OR & 0 \\
 XOR  & Logical XOR & 0 \\
 MUL  & Arithmetical multiplication & 0 \\
-DIV  & Arithmetical division (inc. modulus) & 0 \\
+DIV  & Arithmetical division (inc. modulo) & 0 \\
 
 
 \arrayrulecolor{black}\hline
@@ -152,7 +152,7 @@ INTRE& Set interrupt entry pointer & 2 \\\hline
 	MULLO& Get Arithmetical multiplication of ALU sources (low byte) \\
 	MULHI& Get Arithmetical multiplication of ALU sources (high byte) \\
 	DIV  & Get Arithmetical division of ALU sources \\
-	MOD  & Get Arithmetical modulus of ALU sources \\\hline
+	MOD  & Get Arithmetical modulo of ALU sources \\\hline
 	
 	EQ   & Check if ALU source A is equal to source B \\
 	GT   & Check if ALU source A is greater than source B \\

docs/final_report/index.tex

@@ -89,7 +89,8 @@
 			
 			\Large \emph{Author:}\\
 			Mindaugas \textsc{Jarmolovi\v{c}ius}\\
-			\href{mailto:zceemja@ucl.ac.uk}{zceemja@ucl.ac.uk}\\
+			\href{mailto:zceemja@ucl.ac.uk}{zceemja@ucl.ac.uk}\\[0.3cm]
+			\normalsize{\textbf{SN:} 17139494}
 			
 			\columnbreak
 			
@@ -109,31 +110,28 @@
 		\setstretch{2.5}
 		{ \large \bfseries A BEng Project Final Report}\\[1cm]
 		\setstretch{1.0}
-		{\large March 27, 2020}\\[2cm]
+		{\large\today}\\[2cm]
 		
 	\end{titlepage}
 	
 	\pagebreak
-	\section*{Abstract}\label{sec:abstract}
-	\input{1-abstract.tex}
-	\vspace*{10cm}
 	\tableofcontents
-	\vfill\null\pagebreak
-	
+	\pagebreak
+	\section{Abstract}\label{sec:abstract}
+	\input{1-abstract.tex}
 	
 	\section{Introduction}\label{sec:introduction}
 	\input{2-introduction.tex}
-	\vfill\pagebreak
+
 	\section{Goals and Objectives}\label{sec:objectives}
 	\input{3-objectives.tex}
 
 	\section{Theory and Analytical Bases}\label{sec:theory}
 	\input{4-theory.tex}
-	\vfill\pagebreak
-	
+	\pagebreak
 	\section{Technical Method}\label{sec:methods}
 	\input{5-methods.tex}
-	\vfill\pagebreak
+	
 	\section{Results and Analysis}\label{sec:results}
 	\input{6-results.tex}
 

docs/final_report/index.toc

@@ -1,107 +1,117 @@
 \boolfalse {citerequest}\boolfalse {citetracker}\boolfalse {pagetracker}\boolfalse {backtracker}\relax 
 \defcounter {refsection}{0}\relax 
-\contentsline {section}{\numberline {1}Introduction}{2}{section.1}% 
+\contentsline {section}{\numberline {1}Abstract}{2}{section.1}% 
 \defcounter {refsection}{0}\relax 
-\contentsline {subsection}{\numberline {1.1}Aims and Objectives}{2}{subsection.1.1}% 
+\contentsline {section}{\numberline {2}Introduction}{2}{section.2}% 
 \defcounter {refsection}{0}\relax 
-\contentsline {subsection}{\numberline {1.2}Supporting Theory}{2}{subsection.1.2}% 
+\contentsline {subsection}{\numberline {2.1}Aims and Objectives}{2}{subsection.2.1}% 
 \defcounter {refsection}{0}\relax 
-\contentsline {subsection}{\numberline {1.3}Project contents}{3}{subsection.1.3}% 
+\contentsline {subsection}{\numberline {2.2}Related Work}{2}{subsection.2.2}% 
 \defcounter {refsection}{0}\relax 
-\contentsline {section}{\numberline {2}Goals and Objectives}{4}{section.2}% 
+\contentsline {subsection}{\numberline {2.3}Project contents}{3}{subsection.2.3}% 
 \defcounter {refsection}{0}\relax 
-\contentsline {subsection}{\numberline {2.1}RISC Processor}{4}{subsection.2.1}% 
+\contentsline {section}{\numberline {3}Goals and Objectives}{3}{section.3}% 
 \defcounter {refsection}{0}\relax 
-\contentsline {subsection}{\numberline {2.2}OISC Processor}{4}{subsection.2.2}% 
+\contentsline {subsection}{\numberline {3.1}RISC Processor}{4}{subsection.3.1}% 
 \defcounter {refsection}{0}\relax 
-\contentsline {subsection}{\numberline {2.3}Design Criteria}{4}{subsection.2.3}% 
+\contentsline {subsection}{\numberline {3.2}OISC Processor}{4}{subsection.3.2}% 
 \defcounter {refsection}{0}\relax 
-\contentsline {subsection}{\numberline {2.4}Benchmark}{4}{subsection.2.4}% 
+\contentsline {subsection}{\numberline {3.3}Design Criteria}{4}{subsection.3.3}% 
 \defcounter {refsection}{0}\relax 
-\contentsline {section}{\numberline {3}Theory and Analytical Bases}{4}{section.3}% 
+\contentsline {subsection}{\numberline {3.4}Benchmark}{4}{subsection.3.4}% 
 \defcounter {refsection}{0}\relax 
-\contentsline {subsection}{\numberline {3.1}RISC Processor}{4}{subsection.3.1}% 
+\contentsline {section}{\numberline {4}Theory and Analytical Bases}{4}{section.4}% 
+\defcounter {refsection}{0}\relax 
+\contentsline {subsection}{\numberline {4.1}RISC Processor}{4}{subsection.4.1}% 
+\defcounter {refsection}{0}\relax 
+\contentsline {subsubsection}{\numberline {4.1.1}Pipelining}{5}{subsubsection.4.1.1}% 
+\defcounter {refsection}{0}\relax 
+\contentsline {subsubsection}{\numberline {4.1.2}Multiple cores}{5}{subsubsection.4.1.2}% 
+\defcounter {refsection}{0}\relax 
+\contentsline {subsection}{\numberline {4.2}OISC Processor}{6}{subsection.4.2}% 
+\defcounter {refsection}{0}\relax 
+\contentsline {subsubsection}{\numberline {4.2.1}OISC Pipelining}{6}{subsubsection.4.2.1}% 
 \defcounter {refsection}{0}\relax 
-\contentsline {subsubsection}{\numberline {3.1.1}Pipelining}{5}{subsubsection.3.1.1}% 
+\contentsline {subsection}{\numberline {4.3}Predictions}{6}{subsection.4.3}% 
 \defcounter {refsection}{0}\relax 
-\contentsline {subsubsection}{\numberline {3.1.2}Multiple cores}{6}{subsubsection.3.1.2}% 
+\contentsline {subsubsection}{\numberline {4.3.1}Execution time}{7}{subsubsection.4.3.1}% 
 \defcounter {refsection}{0}\relax 
-\contentsline {subsection}{\numberline {3.2}OISC Processor}{6}{subsection.3.2}% 
+\contentsline {subsubsection}{\numberline {4.3.2}Instruction Space}{7}{subsubsection.4.3.2}% 
 \defcounter {refsection}{0}\relax 
-\contentsline {subsection}{\numberline {3.3}Predictions}{6}{subsection.3.3}% 
+\contentsline {subsubsection}{\numberline {4.3.3}Resources}{7}{subsubsection.4.3.3}% 
 \defcounter {refsection}{0}\relax 
-\contentsline {section}{\numberline {4}Technical Method}{7}{section.4}% 
+\contentsline {section}{\numberline {5}Technical Method}{7}{section.5}% 
 \defcounter {refsection}{0}\relax 
-\contentsline {subsection}{\numberline {4.1}Machine Code}{7}{subsection.4.1}% 
+\contentsline {subsection}{\numberline {5.1}Machine Code}{7}{subsection.5.1}% 
 \defcounter {refsection}{0}\relax 
-\contentsline {subsubsection}{\numberline {4.1.1}RISC}{7}{subsubsection.4.1.1}% 
+\contentsline {subsubsection}{\numberline {5.1.1}RISC Machine Code}{7}{subsubsection.5.1.1}% 
 \defcounter {refsection}{0}\relax 
-\contentsline {subsubsection}{\numberline {4.1.2}OISC}{7}{subsubsection.4.1.2}% 
+\contentsline {subsubsection}{\numberline {5.1.2}OISC Machine Code}{8}{subsubsection.5.1.2}% 
 \defcounter {refsection}{0}\relax 
-\contentsline {subsection}{\numberline {4.2}Data flow}{8}{subsection.4.2}% 
+\contentsline {subsection}{\numberline {5.2}Data flow}{9}{subsection.5.2}% 
 \defcounter {refsection}{0}\relax 
-\contentsline {subsubsection}{\numberline {4.2.1}RISC Datapath}{8}{subsubsection.4.2.1}% 
+\contentsline {subsubsection}{\numberline {5.2.1}RISC Datapath}{9}{subsubsection.5.2.1}% 
 \defcounter {refsection}{0}\relax 
-\contentsline {subsubsection}{\numberline {4.2.2}OISC Datapath}{9}{subsubsection.4.2.2}% 
+\contentsline {subsubsection}{\numberline {5.2.2}OISC Datapath}{10}{subsubsection.5.2.2}% 
 \defcounter {refsection}{0}\relax 
-\contentsline {subsubsection}{\numberline {4.2.3}OISC Datapath Implementation Problems}{9}{subsubsection.4.2.3}% 
+\contentsline {subsubsection}{\numberline {5.2.3}OISC Datapath Implementation Problems}{10}{subsubsection.5.2.3}% 
 \defcounter {refsection}{0}\relax 
-\contentsline {subsection}{\numberline {4.3}Stack}{9}{subsection.4.3}% 
+\contentsline {subsection}{\numberline {5.3}Stack}{10}{subsection.5.3}% 
 \defcounter {refsection}{0}\relax 
-\contentsline {subsubsection}{\numberline {4.3.1}RISC Stack}{9}{subsubsection.4.3.1}% 
+\contentsline {subsubsection}{\numberline {5.3.1}RISC Stack}{11}{subsubsection.5.3.1}% 
 \defcounter {refsection}{0}\relax 
-\contentsline {subsubsection}{\numberline {4.3.2}OISC Stack}{10}{subsubsection.4.3.2}% 
+\contentsline {subsubsection}{\numberline {5.3.2}OISC Stack}{11}{subsubsection.5.3.2}% 
 \defcounter {refsection}{0}\relax 
-\contentsline {subsection}{\numberline {4.4}Program Counters}{10}{subsection.4.4}% 
+\contentsline {subsection}{\numberline {5.4}Program Counters}{11}{subsection.5.4}% 
 \defcounter {refsection}{0}\relax 
-\contentsline {subsubsection}{\numberline {4.4.1}RISC Program Counter}{10}{subsubsection.4.4.1}% 
+\contentsline {subsubsection}{\numberline {5.4.1}RISC Program Counter}{11}{subsubsection.5.4.1}% 
 \defcounter {refsection}{0}\relax 
-\contentsline {subsubsection}{\numberline {4.4.2}OISC Program Counter}{11}{subsubsection.4.4.2}% 
+\contentsline {subsubsection}{\numberline {5.4.2}OISC Program Counter}{12}{subsubsection.5.4.2}% 
 \defcounter {refsection}{0}\relax 
-\contentsline {subsection}{\numberline {4.5}Arithmetic Logic Unit}{12}{subsection.4.5}% 
+\contentsline {subsection}{\numberline {5.5}Arithmetic Logic Unit}{13}{subsection.5.5}% 
 \defcounter {refsection}{0}\relax 
-\contentsline {subsubsection}{\numberline {4.5.1}OISC ALU}{12}{subsubsection.4.5.1}% 
+\contentsline {subsubsection}{\numberline {5.5.1}OISC ALU}{13}{subsubsection.5.5.1}% 
 \defcounter {refsection}{0}\relax 
-\contentsline {subsubsection}{\numberline {4.5.2}RISC ALU}{12}{subsubsection.4.5.2}% 
+\contentsline {subsubsection}{\numberline {5.5.2}RISC ALU}{14}{subsubsection.5.5.2}% 
 \defcounter {refsection}{0}\relax 
-\contentsline {subsection}{\numberline {4.6}Program Memory}{13}{subsection.4.6}% 
+\contentsline {subsection}{\numberline {5.6}Program Memory}{14}{subsection.5.6}% 
 \defcounter {refsection}{0}\relax 
-\contentsline {subsubsection}{\numberline {4.6.1}RISC Program Memory}{13}{subsubsection.4.6.1}% 
+\contentsline {subsubsection}{\numberline {5.6.1}RISC Program Memory}{14}{subsubsection.5.6.1}% 
 \defcounter {refsection}{0}\relax 
-\contentsline {subsubsection}{\numberline {4.6.2}OISC Program Memory}{13}{subsubsection.4.6.2}% 
+\contentsline {subsubsection}{\numberline {5.6.2}OISC Program Memory}{15}{subsubsection.5.6.2}% 
 \defcounter {refsection}{0}\relax 
-\contentsline {subsection}{\numberline {4.7}Instruction decoding}{14}{subsection.4.7}% 
+\contentsline {subsection}{\numberline {5.7}Instruction decoding}{15}{subsection.5.7}% 
 \defcounter {refsection}{0}\relax 
-\contentsline {subsubsection}{\numberline {4.7.1}RISC}{14}{subsubsection.4.7.1}% 
+\contentsline {subsubsection}{\numberline {5.7.1}RISC IMO}{15}{subsubsection.5.7.1}% 
 \defcounter {refsection}{0}\relax 
-\contentsline {subsubsection}{\numberline {4.7.2}OISC}{14}{subsubsection.4.7.2}% 
+\contentsline {subsubsection}{\numberline {5.7.2}OISC Instruction decoding}{16}{subsubsection.5.7.2}% 
 \defcounter {refsection}{0}\relax 
-\contentsline {subsection}{\numberline {4.8}Assembly}{15}{subsection.4.8}% 
+\contentsline {subsection}{\numberline {5.8}Assembly}{16}{subsection.5.8}% 
 \defcounter {refsection}{0}\relax 
-\contentsline {subsection}{\numberline {4.9}System setup}{17}{subsection.4.9}% 
+\contentsline {subsection}{\numberline {5.9}System setup}{18}{subsection.5.9}% 
 \defcounter {refsection}{0}\relax 
-\contentsline {section}{\numberline {5}Results and Analysis}{18}{section.5}% 
+\contentsline {section}{\numberline {6}Results and Analysis}{19}{section.6}% 
 \defcounter {refsection}{0}\relax 
-\contentsline {subsection}{\numberline {5.1}FPGA logic component composition}{18}{subsection.5.1}% 
+\contentsline {subsection}{\numberline {6.1}FPGA logic component composition}{19}{subsection.6.1}% 
 \defcounter {refsection}{0}\relax 
-\contentsline {subsection}{\numberline {5.2}Power analysis}{19}{subsection.5.2}% 
+\contentsline {subsection}{\numberline {6.2}Power analysis}{20}{subsection.6.2}% 
 \defcounter {refsection}{0}\relax 
-\contentsline {subsubsection}{\numberline {5.2.1}Activity Factor}{19}{subsubsection.5.2.1}% 
+\contentsline {subsubsection}{\numberline {6.2.1}Activity Factor}{21}{subsubsection.6.2.1}% 
 \defcounter {refsection}{0}\relax 
-\contentsline {subsection}{\numberline {5.3}Benchmark Programs}{20}{subsection.5.3}% 
+\contentsline {subsection}{\numberline {6.3}Benchmark Programs}{21}{subsection.6.3}% 
 \defcounter {refsection}{0}\relax 
-\contentsline {subsubsection}{\numberline {5.3.1}Instruction composition}{20}{subsubsection.5.3.1}% 
+\contentsline {subsubsection}{\numberline {6.3.1}Instruction composition}{21}{subsubsection.6.3.1}% 
 \defcounter {refsection}{0}\relax 
-\contentsline {subsubsection}{\numberline {5.3.2}Performance}{21}{subsubsection.5.3.2}% 
+\contentsline {subsubsection}{\numberline {6.3.2}Performance}{23}{subsubsection.6.3.2}% 
 \defcounter {refsection}{0}\relax 
-\contentsline {subsubsection}{\numberline {5.3.3}Program space}{23}{subsubsection.5.3.3}% 
+\contentsline {subsubsection}{\numberline {6.3.3}Program space}{24}{subsubsection.6.3.3}% 
 \defcounter {refsection}{0}\relax 
-\contentsline {subsection}{\numberline {5.4}Maximum clock frequency}{23}{subsection.5.4}% 
+\contentsline {subsection}{\numberline {6.4}Maximum clock frequency}{25}{subsection.6.4}% 
 \defcounter {refsection}{0}\relax 
-\contentsline {subsection}{\numberline {5.5}Future work}{24}{subsection.5.5}% 
+\contentsline {subsection}{\numberline {6.5}Future work}{25}{subsection.6.5}% 
 \defcounter {refsection}{0}\relax 
-\contentsline {section}{\numberline {6}Conclusion}{24}{section.6}% 
+\contentsline {section}{\numberline {7}Conclusion}{26}{section.7}% 
 \defcounter {refsection}{0}\relax 
-\contentsline {section}{\numberline {7}Appendix}{26}{section.7}% 
+\contentsline {section}{\numberline {8}Appendix}{29}{section.8}% 
 \defcounter {refsection}{0}\relax 
-\contentsline {subsection}{\numberline {7.1}Processor instruction set tables}{26}{subsection.7.1}% 
+\contentsline {subsection}{\numberline {8.1}Processor instruction set tables}{29}{subsection.8.1}%