Updated ROM

Made instruction rom be more fexible

memory/rom_test.mem

@@ -0,0 +1,16 @@
+00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f
+10 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f
+20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f
+30 31 32 33 34 35 36 37 38 39 3a 3b 3c 3d 3e 3f
+40 41 42 43 44 45 46 47 48 49 4a 4b 4c 4d 4e 4f
+50 51 52 53 54 55 56 57 58 59 5a 5b 5c 5d 5e 5f
+60 61 62 63 64 65 66 67 68 69 6a 6b 6c 6d 6e 6f
+70 71 72 73 74 75 76 77 78 79 7a 7b 7c 7d 7e 7f
+80 81 82 83 84 85 86 87 88 89 8a 8b 8c 8d 8e 8f
+90 91 92 93 94 95 96 97 98 99 9a 9b 9c 9d 9e 9f
+a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 aa ab ac ad ae af
+b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 ba bb bc bd be bf
+c0 c1 c2 c3 c4 c5 c6 c7 c8 c9 ca cb cc cd ce cf
+d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 da db dc dd de df
+e0 e1 e2 e3 e4 e5 e6 e7 e8 e9 ea eb ec ed ee ef
+f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 fa fb fc fd fe ff

src/blocks/instr_mem.sv

@@ -1,27 +1,55 @@
-module instr_mem(addr, instr, imm);
-	parameter IMEM_FILE = "";
-	parameter WIDTH=8, LENGTH=256;
-	localparam ADDR_WIDTH = $clog2(LENGTH);
+module instr_rom(addr, instr);
+	parameter FILE = "";
+	parameter WIDTH=8, LENGTH=256, OUTMUL=2;
+	parameter ADDR_WIDTH = $clog2(LENGTH);
 
-	input  [ADDR_WIDTH-1:0] addr;
-	output [WIDTH-1:0]	imm;
-	output [WIDTH-1:0]	instr;
+	input  wire [ADDR_WIDTH-1:0]   addr;
+	output reg  [WIDTH*OUTMUL-1:0] instr;
 	
 	logic [WIDTH-1:0] rom [LENGTH-1:0];
-	initial $readmemh(IMEM_FILE, rom);
+	initial $readmemh(FILE, rom);
 	initial begin
 		 $display("Instruction ROM dump");
-		 for (int i=0; i < LENGTH; i+=16) begin
+		 for (int i=0; i < LENGTH; i+=32) begin
 			$write("%h:", i);
-			for(int j=0; j<16 && j+i < LENGTH; j++)
+			for(int j=0; j<32 && j+i < LENGTH; j++)
 		 		$write(" %h", rom[i+j]);
 			$display(" :%h", i);
 		end
 	end
  
 	always_comb begin
-		instr = rom[addr];
-		imm = rom[addr + 1];
+		for (int i=0; i<OUTMUL;i++) 
+				instr[WIDTH*i+:WIDTH] = (addr+i >= LENGTH) ? '0 : rom[addr + i];
+	end
+endmodule
+
+`timescale 1ns / 1ns
+module instr_rom_tb;
+	reg [15:0] addr;
+	reg [15:0] instr;
+
+	instr_rom #("../../memory/rom_test.mem", 8, 256, 2, 16) rom0(addr, instr);
+
+	initial begin
+		addr = 'h0000;
+		#10ns;
+		assert(instr == 'h0100);
+		addr = 'h0001;
+		#10ns;
+		assert(instr == 'h0201);
+		addr = 'h0002;
+		#10ns;
+		assert(instr == 'h0302);
+		addr = 'h0003;
+		#10ns;
+		assert(instr == 'h0403);
+		addr = 'h00ff;
+		#10ns;
+		assert(instr == 'h00ff);
+		addr = 'haaff;
+		#10ns;
+		assert(instr == 'h0000);
 	end
 
 endmodule