Project update

Made a bunch of changes that did not passed modelsim compiling. Finishg
minor misconnections and type issues. Added program counter in datapath.
This version can be simulated on modelsim with some instructions.

memory/risc8_test.asm

@@ -0,0 +1,4 @@
+COPY 0 15
+COPY 1 10
+ADD  0 1
+

simulation/modelsim/UCL_project_y3_run_msim_rtl_verilog.do

@@ -11,14 +11,23 @@ vlog -sv -work work +incdir+/home/min/devel/fpga/ucl_project_y3/quartus {/home/m
 vlog -sv -work work +incdir+/home/min/devel/fpga/ucl_project_y3/db {/home/min/devel/fpga/ucl_project_y3/db/pll_clk_altpll.v}
 vlog -sv -work work +incdir+/home/min/devel/fpga/ucl_project_y3/src {/home/min/devel/fpga/ucl_project_y3/src/project.sv}
 vlog -sv -work work +incdir+/home/min/devel/fpga/ucl_project_y3/src/blocks {/home/min/devel/fpga/ucl_project_y3/src/blocks/sdram_control.sv}
+vlog -sv -work work +incdir+/home/min/devel/fpga/ucl_project_y3/src/blocks {/home/min/devel/fpga/ucl_project_y3/src/blocks/instr_mem.sv}
 vlog -sv -work work +incdir+/home/min/devel/fpga/ucl_project_y3/src/blocks {/home/min/devel/fpga/ucl_project_y3/src/blocks/reg_file.sv}
-vlog -sv -work work +incdir+/home/min/devel/fpga/ucl_project_y3/src {/home/min/devel/fpga/ucl_project_y3/src/top.sv}
 vlog -sv -work work +incdir+/home/min/devel/fpga/ucl_project_y3/src/blocks {/home/min/devel/fpga/ucl_project_y3/src/blocks/alu.sv}
+vlog -sv -work work +incdir+/home/min/devel/fpga/ucl_project_y3/src {/home/min/devel/fpga/ucl_project_y3/src/top.sv}
 vlog -sv -work work +incdir+/home/min/devel/fpga/ucl_project_y3/src/risc {/home/min/devel/fpga/ucl_project_y3/src/risc/general.sv}
-vlog -sv -work work +incdir+/home/min/devel/fpga/ucl_project_y3/src/risc {/home/min/devel/fpga/ucl_project_y3/src/risc/cpu.sv}
 vlog -sv -work work +incdir+/home/min/devel/fpga/ucl_project_y3/src/risc {/home/min/devel/fpga/ucl_project_y3/src/risc/datapath.sv}
+vlog -sv -work work +incdir+/home/min/devel/fpga/ucl_project_y3/src/risc {/home/min/devel/fpga/ucl_project_y3/src/risc/cpu.sv}
 vlog -sv -work work +incdir+/home/min/devel/fpga/ucl_project_y3/src/risc {/home/min/devel/fpga/ucl_project_y3/src/risc/controller.sv}
 
+vlog -sv -work work +incdir+/home/min/devel/fpga/ucl_project_y3/src/blocks {/home/min/devel/fpga/ucl_project_y3/src/blocks/alu.sv}
+vlog -sv -work work +incdir+/home/min/devel/fpga/ucl_project_y3/src/blocks {/home/min/devel/fpga/ucl_project_y3/src/blocks/instr_mem.sv}
+vlog -sv -work work +incdir+/home/min/devel/fpga/ucl_project_y3/src/blocks {/home/min/devel/fpga/ucl_project_y3/src/blocks/memory.sv}
+vlog -sv -work work +incdir+/home/min/devel/fpga/ucl_project_y3/src/blocks {/home/min/devel/fpga/ucl_project_y3/src/blocks/sdram_control.sv}
+vlog -sv -work work +incdir+/home/min/devel/fpga/ucl_project_y3/src/risc {/home/min/devel/fpga/ucl_project_y3/src/risc/general.sv}
+vlog -sv -work work +incdir+/home/min/devel/fpga/ucl_project_y3/src/risc {/home/min/devel/fpga/ucl_project_y3/src/risc/controller.sv}
+vlog -sv -work work +incdir+/home/min/devel/fpga/ucl_project_y3/src/risc {/home/min/devel/fpga/ucl_project_y3/src/risc/datapath.sv}
+vlog -sv -work work +incdir+/home/min/devel/fpga/ucl_project_y3/src/risc {/home/min/devel/fpga/ucl_project_y3/src/risc/cpu.sv}
 
 vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs="+acc"  testbench_1
 

simulation/modelsim/risc8_tb_wave.do

@@ -0,0 +1,31 @@
+clk = St1
+rst = St0
+interrupt = HiZ
+com_rd = zzzzzzzz
+imm = xxxxxx
+com_wr = xxxxxxxx
+com_addr = xxxxxxxx
+mem_rd = xxxxxxxxxxxxxxxx
+mem_wr = zzzzzzzzzzzzzzzz
+pc = 4
+r1 = 15
+r2 = 10
+reg_wr = 0
+srcA = 15
+srcB = 10
+alu_rlo = 0
+alu_rhi = x
+cout = x
+cin = x
+alu_eq = x
+alu_gt = x
+alu_zero = 1
+alu_srcA = HiZ
+alu_srcB = HiZ
+alu_op = HiZ
+bconst = 0
+pc_off = 00000001
+pcn = 0000000000000101
+pca = 0000000000000100
+interrupt_flag = 00000000
+#implicit-wire#0 = Not Loggable

src/blocks/alu.sv

@@ -65,8 +65,8 @@ module alu(
 
 	logic [WORD-1:0] radd, rsub, r_low;
 	logic [WORD*2-1:0] rmul, rdiv;
-	assign {radd,cout0} = a + b + cin;
-	assign {rsub,cout1} = a - b - cin;
+	assign {cout0,radd} = a + b + cin;
+	assign {cout1,rsub} = a - b - cin;
 	assign rmul = a * b;
 	assign rdiv = {a/b,a%b};
   	assign r_high = (op == ALU_MUL) ? rmul[15:8] : rdiv[15:8];
@@ -102,7 +102,7 @@ endmodule
 `timescale 1ns / 1ns
 module alu_tb;
 	e_alu_op op;
-	reg [7:0]a, b, r;
+	reg [7:0]a, b, r, rh, rhe;
 	logic overflow, zero, cin, cout, gt, eq, sign;
 	
 	
@@ -117,7 +117,9 @@ module alu_tb;
 		.gt(gt),
 		.eq(eq),
 		.sign(sign),
-		.overflow(overflow)
+		.overflow(overflow),
+		.r_high(rh),
+		.r_high_en(rhe)
 	);
 
 	// Test & print result
@@ -156,7 +158,7 @@ module alu_tb;
 			end
 			
 			$display("ALU Test %4t00ps: %s %8s %s=%s C=%b O=%b", 
-				$time, s_a, "unknown op", s_b, s_r, cout, overflow);
+				$time, s_a, t_op.name(), s_b, s_r, cout, overflow);
 			if (r != t_e || cout != e_c || overflow != e_o) begin 
 				$error("Incorrect: expected R=%s C=%b O=%b", s_e, e_c, e_o);
 			end

src/project.sv

@@ -56,18 +56,17 @@ module com_block(
 
 	always_ff@(posedge clk) begin
 		if(addr == 8'h06) leds <= in_data;
-		if(addr == 8'h05) tx_byte <= in_data;
-		if(addr == 8'h05) uart0_transmit <= 1;
-		else uart0_transmit <= 0; 
 	end
 
 	always_comb begin
-	case(addr)
+		uart0_transmit = (addr == 8'h05) ? 1 : 0;
+		tx_byte = in_data;
+		case(addr)
 			8'h04: out_data = {5'b0, uart0_reg};
 			8'h05: out_data = {5'b0, uart0_reg};
 			8'h07: out_data = {4'b0, switches};
 			default: out_data = 0;
-	endcase
+		endcase
 	end
 endmodule
 

src/risc/controller.csv

@@ -1,50 +1,50 @@
- instr, cdi.alu_op, cdi.selb, cdi.rw_en, cdi.selr, mem_rd, mem_wr
-     MOVE,   ALU_NONE,      SB_NONE,         1,     SR_COM,      0,      0
-     CPY0,   ALU_NONE,       SB_IMM,         1,     SR_IMM,      0,      0
-     CPY1,   ALU_NONE,       SB_IMM,         1,     SR_IMM,      0,      0
-     CPY2,   ALU_NONE,       SB_IMM,         1,     SR_IMM,      0,      0
-     CPY3,   ALU_NONE,       SB_IMM,         1,     SR_IMM,      0,      0
-         ,           ,             ,          ,           ,      0,      0
-      ADD,    ALU_ADD,       SB_REG,         1,    SR_ALUL,      0,      0
-      SUB,    ALU_SUB,       SB_REG,         1,    SR_ALUL,      0,      0
-      AND,    ALU_AND,       SB_REG,         1,    SR_ALUL,      0,      0
-       OR,     ALU_OR,       SB_REG,         1,    SR_ALUL,      0,      0
-      XOR,    ALU_XOR,       SB_REG,         1,    SR_ALUL,      0,      0
-      MUL,    ALU_MUL,       SB_REG,         1,    SR_ALUL,      0,      0
-      DIV,    ALU_DIV,       SB_REG,         1,    SR_ALUL,      0,      0
-       BR,   ALU_NONE,      SB_NONE,         x,    SR_NONE,      0,      0
-         ,           ,             ,          ,           ,      0,      0
-      SLL,     ALU_SL,       SB_REG,         1,    SR_ALUL,      0,      0
-      SRL,     ALU_SR,       SB_REG,         1,    SR_ALUL,      0,      0
-      SRA,     ALU_RA,       SB_REG,         1,    SR_ALUL,      0,      0
-     SRAS,    ALU_RAS,       SB_REG,         1,    SR_ALUL,      0,      0
-         ,           ,             ,          ,           ,      0,      0
-     LWHI,   ALU_NONE,      SB_NONE,         1,    SR_MEMH,      0,      1
-     SWHI,   ALU_NONE,      SB_NONE,         0,    SR_NONE,      1,      0
-     LWLO,   ALU_NONE,      SB_NONE,         1,    SR_MEML,      0,      1
-     SWLO,   ALU_NONE,      SB_NONE,         0,    SR_NONE,      1,      0
-         ,           ,             ,          ,           ,      0,      0
-      INC,    ALU_ADD,         SB_1,         1,    SR_ALUL,      0,      0
-      DEC,    ALU_SUB,         SB_1,         1,    SR_ALUL,      0,      0
-    GETAH,   ALU_NONE,      SB_NONE,         1,    SR_ALUH,      0,      0
-    GETIF,   ALU_NONE,      SB_NONE,         1,    SR_INTR,      0,      0
-         ,           ,             ,          ,           ,      0,      0
-     PUSH,   ALU_NONE,      SB_NONE,         x,    SR_NONE,      0,      0
-      POP,   ALU_NONE,      SB_NONE,         x,    SR_NONE,      0,      0
-      COM,   ALU_NONE,      SB_NONE,         x,    SR_NONE,      0,      0
-         ,           ,             ,          ,           ,      0,      0
-     CALL,   ALU_NONE,      SB_NONE,         x,    SR_NONE,      0,      0
-      RET,   ALU_NONE,      SB_NONE,         x,    SR_NONE,      0,      0
-     JUMP,   ALU_NONE,      SB_NONE,         x,    SR_NONE,      0,      0
-     RETI,   ALU_NONE,      SB_NONE,         x,    SR_NONE,      0,      0
-      CLC,   ALU_NONE,      SB_NONE,         x,    SR_NONE,      0,      0
-     SETC,   ALU_NONE,      SB_NONE,         x,    SR_NONE,      0,      0
-      CLS,   ALU_NONE,      SB_NONE,         x,    SR_NONE,      0,      0
-     SETS,   ALU_NONE,      SB_NONE,         x,    SR_NONE,      0,      0
-    SSETS,   ALU_NONE,      SB_NONE,         x,    SR_NONE,      0,      0
-      CLN,   ALU_NONE,      SB_NONE,         x,    SR_NONE,      0,      0
-     SETN,   ALU_NONE,      SB_NONE,         x,    SR_NONE,      0,      0
-    SSETN,   ALU_NONE,      SB_NONE,         x,    SR_NONE,      0,      0
-    RJUMP,   ALU_NONE,      SB_NONE,         x,    SR_NONE,      0,      0
-     RBWI,   ALU_NONE,      SB_NONE,         x,    SR_NONE,      0,      0
-  default,   ALU_NONE,      SB_NONE,         x,    SR_NONE,      0,      0
+instr,cdi.alu_op,cdi.selb,cdi.rw_en,cdi.selr,mem_rd,mem_wr,cdi.isize
+CPY0,ALU_NONE,SB_IMM,1,SR_IMM,0,0,1
+CPY1,ALU_NONE,SB_IMM,1,SR_IMM,0,0,1
+CPY2,ALU_NONE,SB_IMM,1,SR_IMM,0,0,1
+CPY3,ALU_NONE,SB_IMM,1,SR_IMM,0,0,1
+MOVE,ALU_NONE,SB_NONE,1,SR_COM,0,0,0
+,,,,,,,
+ADD,ALU_ADD,SB_REG,1,SR_ALUL,0,0,0
+SUB,ALU_SUB,SB_REG,1,SR_ALUL,0,0,0
+AND,ALU_AND,SB_REG,1,SR_ALUL,0,0,0
+OR,ALU_OR,SB_REG,1,SR_ALUL,0,0,0
+XOR,ALU_XOR,SB_REG,1,SR_ALUL,0,0,0
+MUL,ALU_MUL,SB_REG,1,SR_ALUL,0,0,0
+DIV,ALU_DIV,SB_REG,1,SR_ALUL,0,0,0
+BR,ALU_NONE,SB_NONE,0,SR_NONE,0,0,2
+,,,,,,,
+SLL,ALU_SL,SB_REG,1,SR_ALUL,0,0,0
+SRL,ALU_SR,SB_REG,1,SR_ALUL,0,0,0
+SRA,ALU_RA,SB_REG,1,SR_ALUL,0,0,0
+SRAS,ALU_RAS,SB_REG,1,SR_ALUL,0,0,0
+,,,,,,,
+LWHI,ALU_NONE,SB_NONE,1,SR_MEMH,0,1,3
+SWHI,ALU_NONE,SB_NONE,0,SR_NONE,1,0,3
+LWLO,ALU_NONE,SB_NONE,1,SR_MEML,0,1,3
+SWLO,ALU_NONE,SB_NONE,0,SR_NONE,1,0,3
+,,,,,,,
+INC,ALU_ADD,SB_1,1,SR_ALUL,0,0,0
+DEC,ALU_SUB,SB_1,1,SR_ALUL,0,0,0
+GETAH,ALU_NONE,SB_NONE,1,SR_ALUH,0,0,0
+GETIF,ALU_NONE,SB_NONE,1,SR_INTR,0,0,0
+,,,,,,,
+PUSH,ALU_NONE,SB_NONE,0,SR_NONE,0,0,0
+POP,ALU_NONE,SB_NONE,1,SR_NONE,0,0,0
+COM,ALU_NONE,SB_NONE,1,SR_NONE,0,0,1
+,,,,,,,
+CALL,ALU_NONE,SB_NONE,0,SR_NONE,0,0,2
+RET,ALU_NONE,SB_NONE,0,SR_NONE,0,0,0
+JUMP,ALU_NONE,SB_NONE,0,SR_NONE,0,0,2
+RETI,ALU_NONE,SB_NONE,0,SR_NONE,0,0,0
+CLC,ALU_NONE,SB_NONE,0,SR_NONE,0,0,0
+SETC,ALU_NONE,SB_NONE,0,SR_NONE,0,0,0
+CLS,ALU_NONE,SB_NONE,0,SR_NONE,0,0,0
+SETS,ALU_NONE,SB_NONE,0,SR_NONE,0,0,0
+SSETS,ALU_NONE,SB_NONE,0,SR_NONE,0,0,0
+CLN,ALU_NONE,SB_NONE,0,SR_NONE,0,0,0
+SETN,ALU_NONE,SB_NONE,0,SR_NONE,0,0,0
+SSETN,ALU_NONE,SB_NONE,0,SR_NONE,0,0,0
+RJUMP,ALU_NONE,SB_NONE,0,SR_NONE,0,0,2
+RBWI,ALU_NONE,SB_NONE,0,SR_NONE,0,0,1
+default,ALU_NONE,SB_NONE,0,SR_NONE,0,0,0

src/risc/controller.sv

@@ -1,3 +1,5 @@
+`define ADDOP
+
 import risc8_pkg::*;
 import alu_pkg::*;
 
@@ -11,19 +13,13 @@ module controller8(
 	assign cdi.a2		= e_reg_addr'(instr[1:0]);
 	assign cdi.a3 		= cdi.a1; // Assuming destination always first operand
 	
+	`ifdef ADDOP 
 	e_instr op;
+	`endif
 
 	// generated table
     always_comb begin
     casez(instr)
-        MOVE   : begin
-            cdi.alu_op = ALU_NONE;
-            cdi.selb   = SB_NONE;
-            cdi.rw_en  = 1;
-            cdi.selr   = SR_COM;
-            mem_rd     = 0;
-            mem_wr     = 0;
-        end
         CPY0   : begin
             cdi.alu_op = ALU_NONE;
             cdi.selb   = SB_IMM;
@@ -31,6 +27,10 @@ module controller8(
             cdi.selr   = SR_IMM;
             mem_rd     = 0;
             mem_wr     = 0;
+            cdi.isize  = 1;
+            `ifdef ADDOP
+            op = CPY0;
+            `endif
         end
         CPY1   : begin
             cdi.alu_op = ALU_NONE;
@@ -39,6 +39,10 @@ module controller8(
             cdi.selr   = SR_IMM;
             mem_rd     = 0;
             mem_wr     = 0;
+            cdi.isize  = 1;
+            `ifdef ADDOP
+            op = CPY1;
+            `endif
         end
         CPY2   : begin
             cdi.alu_op = ALU_NONE;
@@ -47,6 +51,10 @@ module controller8(
             cdi.selr   = SR_IMM;
             mem_rd     = 0;
             mem_wr     = 0;
+            cdi.isize  = 1;
+            `ifdef ADDOP
+            op = CPY2;
+            `endif
         end
         CPY3   : begin
             cdi.alu_op = ALU_NONE;
@@ -55,6 +63,22 @@ module controller8(
             cdi.selr   = SR_IMM;
             mem_rd     = 0;
             mem_wr     = 0;
+            cdi.isize  = 1;
+            `ifdef ADDOP
+            op = CPY3;
+            `endif
+        end
+        MOVE   : begin
+            cdi.alu_op = ALU_NONE;
+            cdi.selb   = SB_NONE;
+            cdi.rw_en  = 1;
+            cdi.selr   = SR_COM;
+            mem_rd     = 0;
+            mem_wr     = 0;
+            cdi.isize  = 0;
+            `ifdef ADDOP
+            op = MOVE;
+            `endif
         end
         ADD    : begin
             cdi.alu_op = ALU_ADD;
@@ -63,6 +87,10 @@ module controller8(
             cdi.selr   = SR_ALUL;
             mem_rd     = 0;
             mem_wr     = 0;
+            cdi.isize  = 0;
+            `ifdef ADDOP
+            op = ADD;
+            `endif
         end
         SUB    : begin
             cdi.alu_op = ALU_SUB;
@@ -71,6 +99,10 @@ module controller8(
             cdi.selr   = SR_ALUL;
             mem_rd     = 0;
             mem_wr     = 0;
+            cdi.isize  = 0;
+            `ifdef ADDOP
+            op = SUB;
+            `endif
         end
         AND    : begin
             cdi.alu_op = ALU_AND;
@@ -79,6 +111,10 @@ module controller8(
             cdi.selr   = SR_ALUL;
             mem_rd     = 0;
             mem_wr     = 0;
+            cdi.isize  = 0;
+            `ifdef ADDOP
+            op = AND;
+            `endif
         end
         OR     : begin
             cdi.alu_op = ALU_OR;
@@ -87,6 +123,10 @@ module controller8(
             cdi.selr   = SR_ALUL;
             mem_rd     = 0;
             mem_wr     = 0;
+            cdi.isize  = 0;
+            `ifdef ADDOP
+            op = OR;
+            `endif
         end
         XOR    : begin
             cdi.alu_op = ALU_XOR;
@@ -95,6 +135,10 @@ module controller8(
             cdi.selr   = SR_ALUL;
             mem_rd     = 0;
             mem_wr     = 0;
+            cdi.isize  = 0;
+            `ifdef ADDOP
+            op = XOR;
+            `endif
         end
         MUL    : begin
             cdi.alu_op = ALU_MUL;
@@ -103,6 +147,10 @@ module controller8(
             cdi.selr   = SR_ALUL;
             mem_rd     = 0;
             mem_wr     = 0;
+            cdi.isize  = 0;
+            `ifdef ADDOP
+            op = MUL;
+            `endif
         end
         DIV    : begin
             cdi.alu_op = ALU_DIV;
@@ -111,14 +159,22 @@ module controller8(
             cdi.selr   = SR_ALUL;
             mem_rd     = 0;
             mem_wr     = 0;
+            cdi.isize  = 0;
+            `ifdef ADDOP
+            op = DIV;
+            `endif
         end
         BR     : begin
             cdi.alu_op = ALU_NONE;
             cdi.selb   = SB_NONE;
-            cdi.rw_en  = 1'bx;
+            cdi.rw_en  = 0;
             cdi.selr   = SR_NONE;
             mem_rd     = 0;
             mem_wr     = 0;
+            cdi.isize  = 2;
+            `ifdef ADDOP
+            op = BR;
+            `endif
         end
         SLL    : begin
             cdi.alu_op = ALU_SL;
@@ -127,6 +183,10 @@ module controller8(
             cdi.selr   = SR_ALUL;
             mem_rd     = 0;
             mem_wr     = 0;
+            cdi.isize  = 0;
+            `ifdef ADDOP
+            op = SLL;
+            `endif
         end
         SRL    : begin
             cdi.alu_op = ALU_SR;
@@ -135,6 +195,10 @@ module controller8(
             cdi.selr   = SR_ALUL;
             mem_rd     = 0;
             mem_wr     = 0;
+            cdi.isize  = 0;
+            `ifdef ADDOP
+            op = SRL;
+            `endif
         end
         SRA    : begin
             cdi.alu_op = ALU_RA;
@@ -143,6 +207,10 @@ module controller8(
             cdi.selr   = SR_ALUL;
             mem_rd     = 0;
             mem_wr     = 0;
+            cdi.isize  = 0;
+            `ifdef ADDOP
+            op = SRA;
+            `endif
         end
         SRAS   : begin
             cdi.alu_op = ALU_RAS;
@@ -151,6 +219,10 @@ module controller8(
             cdi.selr   = SR_ALUL;
             mem_rd     = 0;
             mem_wr     = 0;
+            cdi.isize  = 0;
+            `ifdef ADDOP
+            op = SRAS;
+            `endif
         end
         LWHI   : begin
             cdi.alu_op = ALU_NONE;
@@ -159,6 +231,10 @@ module controller8(
             cdi.selr   = SR_MEMH;
             mem_rd     = 0;
             mem_wr     = 1;
+            cdi.isize  = 3;
+            `ifdef ADDOP
+            op = LWHI;
+            `endif
         end
         SWHI   : begin
             cdi.alu_op = ALU_NONE;
@@ -167,6 +243,10 @@ module controller8(
             cdi.selr   = SR_NONE;
             mem_rd     = 1;
             mem_wr     = 0;
+            cdi.isize  = 3;
+            `ifdef ADDOP
+            op = SWHI;
+            `endif
         end
         LWLO   : begin
             cdi.alu_op = ALU_NONE;
@@ -175,6 +255,10 @@ module controller8(
             cdi.selr   = SR_MEML;
             mem_rd     = 0;
             mem_wr     = 1;
+            cdi.isize  = 3;
+            `ifdef ADDOP
+            op = LWLO;
+            `endif
         end
         SWLO   : begin
             cdi.alu_op = ALU_NONE;
@@ -183,6 +267,10 @@ module controller8(
             cdi.selr   = SR_NONE;
             mem_rd     = 1;
             mem_wr     = 0;
+            cdi.isize  = 3;
+            `ifdef ADDOP
+            op = SWLO;
+            `endif
         end
         INC    : begin
             cdi.alu_op = ALU_ADD;
@@ -191,6 +279,10 @@ module controller8(
             cdi.selr   = SR_ALUL;
             mem_rd     = 0;
             mem_wr     = 0;
+            cdi.isize  = 0;
+            `ifdef ADDOP
+            op = INC;
+            `endif
         end
         DEC    : begin
             cdi.alu_op = ALU_SUB;
@@ -199,6 +291,10 @@ module controller8(
             cdi.selr   = SR_ALUL;
             mem_rd     = 0;
             mem_wr     = 0;
+            cdi.isize  = 0;
+            `ifdef ADDOP
+            op = DEC;
+            `endif
         end
         GETAH  : begin
             cdi.alu_op = ALU_NONE;
@@ -207,6 +303,10 @@ module controller8(
             cdi.selr   = SR_ALUH;
             mem_rd     = 0;
             mem_wr     = 0;
+            cdi.isize  = 0;
+            `ifdef ADDOP
+            op = GETAH;
+            `endif
         end
         GETIF  : begin
             cdi.alu_op = ALU_NONE;
@@ -215,150 +315,223 @@ module controller8(
             cdi.selr   = SR_INTR;
             mem_rd     = 0;
             mem_wr     = 0;
+            cdi.isize  = 0;
+            `ifdef ADDOP
+            op = GETIF;
+            `endif
         end
         PUSH   : begin
             cdi.alu_op = ALU_NONE;
             cdi.selb   = SB_NONE;
-            cdi.rw_en  = 1'bx;
+            cdi.rw_en  = 0;
             cdi.selr   = SR_NONE;
             mem_rd     = 0;
             mem_wr     = 0;
+            cdi.isize  = 0;
+            `ifdef ADDOP
+            op = PUSH;
+            `endif
         end
         POP    : begin
             cdi.alu_op = ALU_NONE;
             cdi.selb   = SB_NONE;
-            cdi.rw_en  = 1'bx;
+            cdi.rw_en  = 1;
             cdi.selr   = SR_NONE;
             mem_rd     = 0;
             mem_wr     = 0;
+            cdi.isize  = 0;
+            `ifdef ADDOP
+            op = POP;
+            `endif
         end
         COM    : begin
             cdi.alu_op = ALU_NONE;
             cdi.selb   = SB_NONE;
-            cdi.rw_en  = 1'bx;
+            cdi.rw_en  = 1;
             cdi.selr   = SR_NONE;
             mem_rd     = 0;
             mem_wr     = 0;
+            cdi.isize  = 1;
+            `ifdef ADDOP
+            op = COM;
+            `endif
         end
         CALL   : begin
             cdi.alu_op = ALU_NONE;
             cdi.selb   = SB_NONE;
-            cdi.rw_en  = 1'bx;
+            cdi.rw_en  = 0;
             cdi.selr   = SR_NONE;
             mem_rd     = 0;
             mem_wr     = 0;
+            cdi.isize  = 2;
+            `ifdef ADDOP
+            op = CALL;
+            `endif
         end
         RET    : begin
             cdi.alu_op = ALU_NONE;
             cdi.selb   = SB_NONE;
-            cdi.rw_en  = 1'bx;
+            cdi.rw_en  = 0;
             cdi.selr   = SR_NONE;
             mem_rd     = 0;
             mem_wr     = 0;
+            cdi.isize  = 0;
+            `ifdef ADDOP
+            op = RET;
+            `endif
         end
         JUMP   : begin
             cdi.alu_op = ALU_NONE;
             cdi.selb   = SB_NONE;
-            cdi.rw_en  = 1'bx;
+            cdi.rw_en  = 0;
             cdi.selr   = SR_NONE;
             mem_rd     = 0;
             mem_wr     = 0;
+            cdi.isize  = 2;
+            `ifdef ADDOP
+            op = JUMP;
+            `endif
         end
         RETI   : begin
             cdi.alu_op = ALU_NONE;
             cdi.selb   = SB_NONE;
-            cdi.rw_en  = 1'bx;
+            cdi.rw_en  = 0;
             cdi.selr   = SR_NONE;
             mem_rd     = 0;
             mem_wr     = 0;
+            cdi.isize  = 0;
+            `ifdef ADDOP
+            op = RETI;
+            `endif
         end
         CLC    : begin
             cdi.alu_op = ALU_NONE;
             cdi.selb   = SB_NONE;
-            cdi.rw_en  = 1'bx;
+            cdi.rw_en  = 0;
             cdi.selr   = SR_NONE;
             mem_rd     = 0;
             mem_wr     = 0;
+            cdi.isize  = 0;
+            `ifdef ADDOP
+            op = CLC;
+            `endif
         end
         SETC   : begin
             cdi.alu_op = ALU_NONE;
             cdi.selb   = SB_NONE;
-            cdi.rw_en  = 1'bx;
+            cdi.rw_en  = 0;
             cdi.selr   = SR_NONE;
             mem_rd     = 0;
             mem_wr     = 0;
+            cdi.isize  = 0;
+            `ifdef ADDOP
+            op = SETC;
+            `endif
         end
         CLS    : begin
             cdi.alu_op = ALU_NONE;
             cdi.selb   = SB_NONE;
-            cdi.rw_en  = 1'bx;
+            cdi.rw_en  = 0;
             cdi.selr   = SR_NONE;
             mem_rd     = 0;
             mem_wr     = 0;
+            cdi.isize  = 0;
+            `ifdef ADDOP
+            op = CLS;
+            `endif
         end
         SETS   : begin
             cdi.alu_op = ALU_NONE;
             cdi.selb   = SB_NONE;
-            cdi.rw_en  = 1'bx;
+            cdi.rw_en  = 0;
             cdi.selr   = SR_NONE;
             mem_rd     = 0;
             mem_wr     = 0;
+            cdi.isize  = 0;
+            `ifdef ADDOP
+            op = SETS;
+            `endif
         end
         SSETS  : begin
             cdi.alu_op = ALU_NONE;
             cdi.selb   = SB_NONE;
-            cdi.rw_en  = 1'bx;
+            cdi.rw_en  = 0;
             cdi.selr   = SR_NONE;
             mem_rd     = 0;
             mem_wr     = 0;
+            cdi.isize  = 0;
+            `ifdef ADDOP
+            op = SSETS;
+            `endif
         end
         CLN    : begin
             cdi.alu_op = ALU_NONE;
             cdi.selb   = SB_NONE;
-            cdi.rw_en  = 1'bx;
+            cdi.rw_en  = 0;
             cdi.selr   = SR_NONE;
             mem_rd     = 0;
             mem_wr     = 0;
+            cdi.isize  = 0;
+            `ifdef ADDOP
+            op = CLN;
+            `endif
         end
         SETN   : begin
             cdi.alu_op = ALU_NONE;
             cdi.selb   = SB_NONE;
-            cdi.rw_en  = 1'bx;
+            cdi.rw_en  = 0;
             cdi.selr   = SR_NONE;
             mem_rd     = 0;
             mem_wr     = 0;
+            cdi.isize  = 0;
+            `ifdef ADDOP
+            op = SETN;
+            `endif
         end
         SSETN  : begin
             cdi.alu_op = ALU_NONE;
             cdi.selb   = SB_NONE;
-            cdi.rw_en  = 1'bx;
+            cdi.rw_en  = 0;
             cdi.selr   = SR_NONE;
             mem_rd     = 0;
             mem_wr     = 0;
+            cdi.isize  = 0;
+            `ifdef ADDOP
+            op = SSETN;
+            `endif
         end
         RJUMP  : begin
             cdi.alu_op = ALU_NONE;
             cdi.selb   = SB_NONE;
-            cdi.rw_en  = 1'bx;
+            cdi.rw_en  = 0;
             cdi.selr   = SR_NONE;
             mem_rd     = 0;
             mem_wr     = 0;
+            cdi.isize  = 2;
+            `ifdef ADDOP
+            op = RJUMP;
+            `endif
         end
         RBWI   : begin
             cdi.alu_op = ALU_NONE;
             cdi.selb   = SB_NONE;
-            cdi.rw_en  = 1'bx;
+            cdi.rw_en  = 0;
             cdi.selr   = SR_NONE;
             mem_rd     = 0;
             mem_wr     = 0;
+            cdi.isize  = 1;
+            `ifdef ADDOP
+            op = RBWI;
+            `endif
         end
         default: begin
             cdi.alu_op = ALU_NONE;
             cdi.selb   = SB_NONE;
-            cdi.rw_en  = 1'bx;
+            cdi.rw_en  = 0;
             cdi.selr   = SR_NONE;
             mem_rd     = 0;
             mem_wr     = 0;
+            cdi.isize  = 0;
         end
     endcase
     end

src/risc/cpu.sv

@@ -16,24 +16,22 @@ import alu_pkg::*;
 //endmodule
 
 module risc8_cpu(processor_port port);
-	//logic clk, rst, mem_wr; 
-	//word pc, instr, imm, mem_addr, mem_data, mem_rd_data;
-	
-	//assign port.ram_wr_en = mem_wr;
-	//assign port.ram_rd_en = ~mem_wr;
-
-	//instr_mem #("/home/min/devel/fpga/ucl_project_y3/memory/test.mem") imem0(pc, instr, imm);
+	parameter PROGRAM="";
+	reg [31:0] instr; // Fetching 4x8bit instruction
+	reg [15:0] pc; // Instruction memory is 16bit in length
+	initial $display("RISC8 program: %s", PROGRAM);	
+	instr_rom #(.FILE(PROGRAM),
+				.LENGTH(256),
+				.OUTMUL(4),
+				.ADDR_WIDTH(16)
+		) rom0 (pc, instr);
 	
 	//risc8_cpu cpu0(port.clk, port.rst, instr, imm, pc,
 	//		port.ram_addr, mem_wr, port.ram_wr_data, port.ram_rd_data);
 	
-	word instr, imm0, imm1, imm2;
-	assign imm0 = 8'h00;
-	assign instr = 8'h00;
-
 	risc8_cdi cdi0();
 	controller8 ctrl0(
-			.instr(instr),
+			.instr(instr[7:0]),
 			.cdi(cdi0),
 			.mem_wr(port.ram_wr_en),
 			.mem_rd(port.ram_rd_en)
@@ -42,27 +40,47 @@ module risc8_cpu(processor_port port);
 			.clk(port.clk),
 			.rst(port.rst),
 			.cdi(cdi0),
-			.imm(imm0),
+			.imm(instr[31:8]),
 			.mem_rd(port.ram_rd_data),
-			.mem_wr(port.ram_wr_data)
+			.mem_wr(port.ram_wr_data),
+			.pc(pc)
 	);
 
 endmodule
 
 `timescale 1ns / 1ns
 module risc8_cpu_tb;
-	logic clk, rst, mem_wr; 
-	word pc, instr, imm, mem_addr, mem_data, mem_rd_data;	
-	cpu CPU(clk, rst, instr, imm, pc, mem_addr, mem_wr, mem_data, mem_rd_data);
-	// Instruction memory
-	instr_mem #("/home/min/devel/fpga/ucl_project_y3/memory/test.mem") IMEM(pc, instr, imm);
-	// System memory
-	memory RAM(clk, mem_wr, mem_addr, mem_data, mem_rd_data);
-	word outvalue;
-	always_ff@(posedge clk) begin
-			if(mem_wr & mem_addr == 8'hFF) outvalue <= mem_data;
-			else outvalue <= 0; 
-	end
+
+	logic clk, rst;
+	logic [23:0] ram_addr;
+	logic [15:0] ram_wr;
+	logic [15:0] ram_rd;
+	logic ram_wr_en;
+	logic ram_rd_en;
+
+	processor_port port0(
+		.clk(clk),
+		.rst(rst),
+		.ram_addr(ram_addr),
+		.ram_wr_data(ram_wr),
+		.ram_rd_data(ram_rd),
+		.ram_wr_en(ram_wr_en),
+		.ram_rd_en(ram_rd_en)
+	);
+	
+	risc8_cpu #(.PROGRAM("../../memory/risc8_test.mem")) cpu0(port0);
+	
+	memory #(
+			.WIDTH(16),
+			.LENGTH(2**24)
+	) ram0 (
+			clk,
+			ram_wr_en,
+			ram_rd_en,
+			ram_addr,
+			ram_wr,
+			ram_rd
+	);
 
 	initial begin
 		clk = 0;

src/risc/datapath.sv

@@ -5,10 +5,12 @@ import alu_pkg::*;
 module datapath8(
 		input logic clk, rst, interrupt,
 		risc8_cdi.datapath cdi,
-		input  word imm, com_rd,
+		input  word com_rd,
+		input  wire [23:0] imm,
 		output word com_wr, com_addr,
 		input  [15:0] mem_rd,
-		output [15:0] mem_wr
+		output [15:0] mem_wr,
+		output reg [15:0] pc
 );
 	
 	word r1, r2, reg_wr;
@@ -24,22 +26,48 @@ module datapath8(
 	);
 
 	word srcA, srcB, alu_rlo, alu_rhi;
-	logic cout, cin, alu_eq, alu_gt, alu_zero;
+	logic cout, cin, alu_eq, alu_gt, alu_zero, alu_sign;
 	assign cdi.alu_comp = {alu_eq, alu_gt, alu_zero};
+	assign alu_sign = 0;
+	always_ff@(posedge clk) begin
+			if(rst) cin <= 0;
+			else if(cdi.alu_op == ALU_ADD || cdi.alu_op == ALU_SUB)
+					cin <= cout;
+	end
 
 	alu#(.WORD(8)) alu0(
-		.a(alu_srcA),
-		.b(alu_srcB),
-		.op(e_alu_op'(alu_op)),
+		.a(srcA),
+		.b(srcB),
+		.op(cdi.alu_op),
 		.r(alu_rlo),
 		.r_high(alu_rhi),
 		.zero(alu_zero),
 		.eq(alu_eq),
 		.gt(alu_gt),
 		.cin(cin), .cout(cout),
-		.sign(cdi.sign)
+		.sign(alu_sign)
 		// TODO: missing overflow
 	);
+
+	// Program counter
+	logic bconst; // Use immediate to branch
+	word pc_off; // Program counter offset
+	reg [15:0] pcn, pca; // Program Counter Previous, to add
+	always_ff@(posedge clk) begin
+			if(rst) pc <= '0; 
+			else pc <= pcn;
+	end
+
+	assign bconst = 0;  // FIXME: temporary
+	assign pca = (bconst) ? imm[15:0] : pc;
+	assign pc_off = { 
+			5'b0000_0, 
+			cdi.isize[0]&cdi.isize[1], 
+			cdi.isize[0]^cdi.isize[1], 
+			(~cdi.isize[1]&~cdi.isize[0])|(cdi.isize[1]&~cdi.isize[0])
+	}; // Adding 1 to 2bit value.
+	assign pcn = pca + pc_off;
+
 	
 	word interrupt_flag;
 	always_ff@(posedge clk) begin
@@ -53,7 +81,7 @@ module datapath8(
 			SB_REG : srcB = r2;
 			SB_0   : srcB = 8'h00;
 			SB_1   : srcB = 8'h01;
-			SB_IMM : srcB = imm;
+			SB_IMM : srcB = imm[7:0];
 			default: srcB = r2;
 		endcase
 
@@ -62,7 +90,7 @@ module datapath8(
 			SR_MEMH: reg_wr = mem_rd[15:8];
 			SR_ALUL: reg_wr = alu_rlo;
 			SR_ALUH: reg_wr = alu_rhi;
-			SR_IMM : reg_wr = imm;
+			SR_IMM : reg_wr = imm[7:0];
 			SR_COM : reg_wr = com_rd;
 			SR_INTR: reg_wr = interrupt_flag;
 			default: reg_wr = alu_rlo;

src/risc/general.sv

@@ -92,6 +92,36 @@ package risc8_pkg;
 
 endpackage
 
+interface risc8_cdi;  // Control Datapath interface	
+	import risc8_pkg::*;
+	import alu_pkg::*;
+
+	// ALU
+	e_alu_op alu_op;
+	logic sign, alu_not;
+	e_selb selb;
+	logic [2:0] alu_comp;
+	
+	// Register
+	reg_addr a1, a2, a3;
+	logic rw_en, mem_h;
+	e_selr selr;
+	logic [1:0] isize; // instruction size between 1 and 4
+	
+	modport datapath(
+		input alu_op, selb, sign, alu_not,
+		output alu_comp,
+		input a1, a2, a3, rw_en, selr, mem_h, isize
+	);
+	
+	modport control(
+		output alu_op, selb, sign, alu_not,
+		input alu_comp,
+		output a1, a2, a3, rw_en, selr, mem_h, isize
+	);
+
+endinterface
+
 package risc8x_pkg;
 		
 	localparam word_size = 8;
@@ -191,33 +221,3 @@ package risc8x_pkg;
 
 endpackage
 
-
-interface risc8_cdi;  // Control Datapath interface	
-	import risc8_pkg::*;
-	import alu_pkg::*;
-
-	// ALU
-	e_alu_op alu_op;
-	logic sign, alu_not;
-	e_selb selb;
-	logic [2:0] alu_comp;
-	
-	// Register
-	reg_addr a1, a2, a3;
-	logic rw_en, mem_h;
-	e_selr selr;
-	
-	modport datapath(
-		input alu_op, selb, sign, alu_not,
-		output alu_comp,
-		input a1, a2, a3, rw_en, selr, mem_h
-	);
-	
-	modport control(
-		output alu_op, selb, sign, alu_not,
-		input alu_comp,
-		output a1, a2, a3, rw_en, selr, mem_h
-	);
-
-endinterface
-

tools/asm_compiler.py

@@ -35,10 +35,16 @@ def decode_byte(val: str):
 def is_reg(r):
     if r.startswith('$'):
         r = r[1:]
-    return len(r) == 2 and (r == 'ra' or r == 'rb' or r == 'rc' or r == 're')
+    if r.isnumeric() and 0 <= int(r) <= 3:
+        return True
+    elif len(r) == 2 and (r == 'ra' or r == 'rb' or r == 'rc' or r == 're'):
+        return True
+    return False
 
 
 def decode_reg(r):
+    if r.isnumeric():
+        r = int(r)
     if isinstance(r, int):
         if 0 <= r <= 3:
             return r

tools/gen_sv.py

@@ -77,6 +77,8 @@ if __name__ == '__main__':
         idata.append(f'\t\t{case.ljust(max_case, " ")}: begin')
         for i, head in enumerate(header):
             idata.append(f'\t\t\t{head.ljust(max_header, " ")} = {value[i]};')
+        if case != 'default':
+            idata.append(f'\t\t\t`ifdef ADDOP\n\t\t\top = {case};\n\t\t\t`endif')
         idata.append('\t\tend')
     idata.append('\tendcase')
     idata.append('\tend')