Impl. BEQ, BGT, BGE instructions

Implemented Branch on {equal, greater than, greater equal than}
instructions. They use imm[0:7] to compare to rd and imm[23:8] as jump
address.

memory/risc8_test.asm

@@ -14,33 +14,36 @@ b1111_0000 // 0x000d Call AddAllBy1
 0x0003
 ADD  r0 r1 // 0x000f
 COPY r0 r2 // 0x0010
-
-SUB  r0 r1
+SUB  r0 r1 
 COPY r0 r2
-
 AND  r0 r1
 COPY r0 r2
-
 OR  r0 r1
 COPY r0 r2
-
 XOR  r0 r1
 COPY r0 r2
-
 COPY r0 100
 MUL  r0 r1
 b1011_1110 // Load ALU_HI to r3
 COPY r0 r2
-
 DIV  r0 r1
 b1011_1110
 DIV  r1 r2
 b1011_1110
-
-b1011_0000 // &r1++
-b1011_0000 // &r1++
-b1011_0001 // &r1--
-b1011_0001 // &r1--
+b1011_0000 // &r0++
+b1011_0000 // &r0++
+b1011_0001 // &r0--
+b1011_0001 // &r0--
+
+b1101_0000 // Branch to 0x000f if r1 == 0
+0x00000f   
+COPY r3 40h
+b1101_1110 // Branch to 0x000f if r1 >= 41h
+0x41000f   
+b1101_1101 // Branch to 0x000f if r1 > 40h
+0x40000f   
+b1101_1110 // Branch to 0x000f if r1 >= 40h
+0x40000f   
 
 COPY r0 32h 
 COPY r1 4fh

src/risc/controller.csv

@@ -27,10 +27,15 @@
     PUSH,   ALU_NONE,  SB_NONE,         0,  SR_NONE,      0,      1,         0,SO_MEML ,  ST_SUB, PC_NONE 
      POP,   ALU_NONE,  SB_NONE,         1,  SR_MEML,      1,      0,         0,SO_MEML ,  ST_ADD, PC_NONE 
      COM,   ALU_NONE,  SB_NONE,         1,   SR_COM,      0,      0,         1, SO_COM , ST_SKIP, PC_NONE 
-    CALL,   ALU_NONE,  SB_NONE,         0,  SR_NONE,      0,      1,         1,SO_MEML ,  ST_SUB, PC_CALL 
-     RET,   ALU_NONE,  SB_NONE,         0,  SR_NONE,      1,      0,         2,SO_MEML ,  ST_ADD,  PC_RET 
-    JUMP,   ALU_NONE,  SB_NONE,         0,  SR_NONE,      0,      0,         1,SO_MEML , ST_NONE, PC_JUMP 
-    RETI,   ALU_NONE,  SB_NONE,         0,  SR_NONE,      1,      0,         2,SO_MEML ,  ST_SUB,  PC_RET 
+    SETI,   ALU_NONE,  SB_NONE,         0,  SR_NONE,      0,      0,         0,SO_MEML , ST_SKIP, PC_NONE 
+     BEQ,   ALU_NONE,   SB_IMM,         0,  SR_NONE,      0,      0,(cdi.alu_comp[2:1] == 'b10)?1:3,SO_MEML , ST_SKIP,(cdi.alu_comp[2:1] == 'b10)?PC_IMM2:PC_NONE
+     BGT,   ALU_NONE,   SB_IMM,         0,  SR_NONE,      0,      0,(cdi.alu_comp[2:1] == 'b01)?1:3,SO_MEML , ST_SKIP,(cdi.alu_comp[2:1] == 'b01)?PC_IMM2:PC_NONE
+     BGE,   ALU_NONE,   SB_IMM,         0,  SR_NONE,      0,      0,(cdi.alu_comp[2]|cdi.alu_comp[1])?1:3,SO_MEML , ST_SKIP,(cdi.alu_comp[2]|cdi.alu_comp[1])?PC_IMM2:PC_NONE
+      BZ,   ALU_NONE,  SB_NONE,         0,  SR_NONE,      0,      0,         0,SO_MEML , ST_SKIP, PC_NONE 
+    CALL,   ALU_NONE,  SB_NONE,         0,  SR_NONE,      0,      1,         1,SO_MEML ,  ST_SUB,  PC_IMM 
+     RET,   ALU_NONE,  SB_NONE,         0,  SR_NONE,      1,      0,         2,SO_MEML ,  ST_ADD,  PC_MEM 
+    JUMP,   ALU_NONE,  SB_NONE,         0,  SR_NONE,      0,      0,         1,SO_MEML , ST_NONE,  PC_IMM
+    RETI,   ALU_NONE,  SB_NONE,         0,  SR_NONE,      1,      0,         2,SO_MEML ,  ST_SUB,  PC_MEM 
      CLC,   ALU_NONE,  SB_NONE,         0,  SR_NONE,      0,      0,         0,SO_MEML , ST_SKIP, PC_NONE 
     SETC,   ALU_NONE,  SB_NONE,         0,  SR_NONE,      0,      0,         0,SO_MEML , ST_SKIP, PC_NONE 
      CLS,   ALU_NONE,  SB_NONE,         0,  SR_NONE,      0,      0,         0,SO_MEML , ST_SKIP, PC_NONE 

src/risc/controller.sv

@@ -440,6 +440,81 @@ module controller8(
             op = COM;
             `endif
         end
+        SETI   : begin
+            cdi.alu_op  = ALU_NONE;
+            cdi.selb    = SB_NONE;
+            cdi.rw_en   = 0;
+            cdi.selr    = SR_NONE;
+            mem_rd      = 0;
+            mem_wr      = 0;
+            cdi.isize   = 0;
+            cdi.selo    = SO_MEML;
+            cdi.stackop = ST_SKIP;
+            cdi.pcop    = PC_NONE;
+            `ifdef ADDOP
+            op = SETI;
+            `endif
+        end
+        BEQ    : begin
+            cdi.alu_op  = ALU_NONE;
+            cdi.selb    = SB_IMM;
+            cdi.rw_en   = 0;
+            cdi.selr    = SR_NONE;
+            mem_rd      = 0;
+            mem_wr      = 0;
+            cdi.isize   = (cdi.alu_comp[2:1] == 'b10)?1:3;
+            cdi.selo    = SO_MEML;
+            cdi.stackop = ST_SKIP;
+            cdi.pcop    = (cdi.alu_comp[2:1] == 'b10)?PC_IMM2:PC_NONE;
+            `ifdef ADDOP
+            op = BEQ;
+            `endif
+        end
+        BGT    : begin
+            cdi.alu_op  = ALU_NONE;
+            cdi.selb    = SB_IMM;
+            cdi.rw_en   = 0;
+            cdi.selr    = SR_NONE;
+            mem_rd      = 0;
+            mem_wr      = 0;
+            cdi.isize   = (cdi.alu_comp[2:1] == 'b01)?1:3;
+            cdi.selo    = SO_MEML;
+            cdi.stackop = ST_SKIP;
+            cdi.pcop    = (cdi.alu_comp[2:1] == 'b01)?PC_IMM2:PC_NONE;
+            `ifdef ADDOP
+            op = BGT;
+            `endif
+        end
+        BGE    : begin
+            cdi.alu_op  = ALU_NONE;
+            cdi.selb    = SB_IMM;
+            cdi.rw_en   = 0;
+            cdi.selr    = SR_NONE;
+            mem_rd      = 0;
+            mem_wr      = 0;
+            cdi.isize   = (cdi.alu_comp[2]|cdi.alu_comp[1])?1:3;
+            cdi.selo    = SO_MEML;
+            cdi.stackop = ST_SKIP;
+            cdi.pcop    = (cdi.alu_comp[2]|cdi.alu_comp[1])?PC_IMM2:PC_NONE;
+            `ifdef ADDOP
+            op = BGE;
+            `endif
+        end
+        BZ     : begin
+            cdi.alu_op  = ALU_NONE;
+            cdi.selb    = SB_NONE;
+            cdi.rw_en   = 0;
+            cdi.selr    = SR_NONE;
+            mem_rd      = 0;
+            mem_wr      = 0;
+            cdi.isize   = 0;
+            cdi.selo    = SO_MEML;
+            cdi.stackop = ST_SKIP;
+            cdi.pcop    = PC_NONE;
+            `ifdef ADDOP
+            op = BZ;
+            `endif
+        end
         CALL   : begin
             cdi.alu_op  = ALU_NONE;
             cdi.selb    = SB_NONE;
@@ -450,7 +525,7 @@ module controller8(
             cdi.isize   = 1;
             cdi.selo    = SO_MEML;
             cdi.stackop = ST_SUB;
-            cdi.pcop    = PC_CALL;
+            cdi.pcop    = PC_IMM;
             `ifdef ADDOP
             op = CALL;
             `endif
@@ -465,7 +540,7 @@ module controller8(
             cdi.isize   = 2;
             cdi.selo    = SO_MEML;
             cdi.stackop = ST_ADD;
-            cdi.pcop    = PC_RET;
+            cdi.pcop    = PC_MEM;
             `ifdef ADDOP
             op = RET;
             `endif
@@ -480,7 +555,7 @@ module controller8(
             cdi.isize   = 1;
             cdi.selo    = SO_MEML;
             cdi.stackop = ST_NONE;
-            cdi.pcop    = PC_JUMP;
+            cdi.pcop    = PC_IMM;
             `ifdef ADDOP
             op = JUMP;
             `endif
@@ -495,7 +570,7 @@ module controller8(
             cdi.isize   = 2;
             cdi.selo    = SO_MEML;
             cdi.stackop = ST_SUB;
-            cdi.pcop    = PC_RET;
+            cdi.pcop    = PC_MEM;
             `ifdef ADDOP
             op = RETI;
             `endif

src/risc/datapath.sv

@@ -73,9 +73,9 @@ module datapath8(
 		bconst = 0;  // FIXME: temporary
 		case(cdi.pcop)
 			PC_NONE: pca = pc;
-			PC_CALL: pca = {imm[7:0], imm[15:8]};
-			PC_RET : pca = mem_rd;
-			PC_JUMP: pca = {imm[7:0], imm[15:8]};
+			PC_MEM : pca = mem_rd;
+			PC_IMM : pca = {imm[7:0], imm[15:8]};
+			PC_IMM2: pca = {imm[15:8], imm[23:16]};
 			default: pca = pc;
 		endcase
 		//pca = (bconst) ? {imm[7:0], imm[15:8]} : pc;
@@ -107,7 +107,7 @@ module datapath8(
 		sp_next = sp + sp_add;
 		sp_addr = {9'b1111_1111_1, (cdi.stackop == ST_ADD) ? sp_next[15:1] : sp[15:1]};
 		st_rd = {mem_rd[7:0]};
-		st_wr = (cdi.pcop == PC_CALL) ? pc : {8'h00, r1};
+		st_wr = (cdi.pcop == PC_IMM) ? pc : {8'h00, r1};
 		//if(sp[0]) begin
 			//st_wr = {'h00, r1};
 			//st_rd = {mem_rd[7:0]};

src/risc/general.sv

@@ -24,7 +24,7 @@ package risc8_pkg;
 		XOR  =8'b0101_????,  // &rd = &rd ^ &rs
 		MUL  =8'b0110_????,  // {&ah,  &rd} = &rd * &rs
 		DIV  =8'b0111_????,  // &rd = &rd / &rs, &ah = &rd % &rs 
-		BR   =8'b1000_????,  // Conditional branch
+		BR   =8'b1000_????,  // FIXME: Conditional branch
 		
 		SLL  =8'b1001_??00,  // i9-0 shift left logical
 		SRL  =8'b1001_??01,  // i9-1 shift right logical
@@ -43,8 +43,14 @@ package risc8_pkg;
 		
 		PUSH =8'b1100_??00,  // i12-0
         POP  =8'b1100_??01,  // i12-1 
-        COM  =8'b1100_??10,  // i12-2 
+        COM  =8'b1100_??10,  // i12-2
+		SETI =8'b1100_??11,  // i12-3 Set next immidate
 		
+		BEQ  =8'b1101_??00,  // i13-0 Branch to imm[24:8] if imm[7:0] == rd
+		BGT  =8'b1101_??01,  // i13-1 Branch greater than
+		BGE  =8'b1101_??10,  // i13-2 Branch greater equal than
+		BZ   =8'b1101_0011,  // i13-3 Branch to imm[15:0] if rd == zero
+
 		CALL =8'b1111_0000,  // i15-0
         RET  =8'b1111_0001,  // i15-1
         JUMP =8'b1111_0010,  // i15-2
@@ -109,10 +115,11 @@ package risc8_pkg;
 
 	typedef enum logic [2:0] {
 		PC_NONE= 3'b000,
-		PC_CALL= 3'b001,
-		PC_RET = 3'b010,
-		PC_RETI= 3'b011,
-		PC_JUMP= 3'b100
+		PC_MEM = 3'b001,
+		PC_IMM = 3'b010,
+		PC_IMM2= 3'b011,
+		PC_MEMI= 3'b100   // TODO: Maybe Memory + interrupt flag?
+
 	} e_pcop;
 
 endpackage