CALL,RET,JUMP instructions

memory/risc8_test.asm

@@ -1,4 +1,83 @@
-COPY 0 15
-COPY 1 10
-ADD  0 1
+b1111_0010 // 0x0000
+0x0007
+b1011_0000 // 0x0003 func AddAllBy1
+b1011_0100 // 0x0004
+b1011_1000 // 0x0005
+b1011_1100 // 0x0006
+b1111_0001 // 0x0007
 
+COPY r0 0x15 // 0x0008
+COPY r2 r0   // 0x000a
+COPY r1 0x0a // 0x000b
+
+b1111_0000 // 0x000d Call AddAllBy1
+0x0002
+ADD  r0 r1 // 0x000f
+COPY r0 r2 // 0x0010
+
+SUB  r0 r1
+COPY r0 r2
+
+AND  r0 r1
+COPY r0 r2
+
+OR  r0 r1
+COPY r0 r2
+
+XOR  r0 r1
+COPY r0 r2
+
+COPY r0 100
+MUL  r0 r1
+b1011_1110 // Load ALU_HI to r3
+COPY r0 r2
+
+DIV  r0 r1
+b1011_1110
+DIV  r1 r2
+b1011_1110
+
+b1011_0000 // &r1++
+b1011_0000 // &r1++
+b1011_0001 // &r1--
+b1011_0001 // &r1--
+
+COPY r0 32h 
+COPY r1 4fh
+b1010_0001  // Store 32 to high memory
+b1010_0111  // Store 4f to low 000001h
+0x010000
+COPY r0 0
+COPY r1 r0
+b1010_0000
+0x010000
+b1010_0010
+0x010000
+
+// Testing COM
+b1100_0010
+ffh
+
+// Testing Stack
+COPY r0 11h
+COPY r1 22h
+COPY r2 33h
+COPY r3 44h
+b1100_0000  // PUSH r0
+b1100_0100  // PUSH r1
+b1100_1000  // PUSH r2
+b1100_1100  // PUSH r3
+COPY r3 55h
+b1100_1100  // PUSH r2
+
+COPY r0 00h
+b1100_0001 // POP r2
+b1100_0001 // POP r2
+b1100_0001 // POP r2
+b1100_0001 // POP r2
+b1100_0001 // POP r2
+
+
+
+b1111_0010 // Reset
+0x0000

src/risc/controller.csv

@@ -1,44 +1,44 @@
-   instr, cdi.alu_op, cdi.selb, cdi.rw_en, cdi.selr, mem_rd, mem_wr, cdi.isize,cdi.selo ,cdi.stackop
-    CPY0,   ALU_NONE,   SB_IMM,         1,   SR_IMM,      0,      0,         1,SO_MEML , ST_SKIP
-    CPY1,   ALU_NONE,   SB_IMM,         1,   SR_IMM,      0,      0,         1,SO_MEML , ST_SKIP
-    CPY2,   ALU_NONE,   SB_IMM,         1,   SR_IMM,      0,      0,         1,SO_MEML , ST_SKIP
-    CPY3,   ALU_NONE,   SB_IMM,         1,   SR_IMM,      0,      0,         1,SO_MEML , ST_SKIP
-    MOVE,   ALU_NONE,  SB_NONE,         1,   SR_REG,      0,      0,         0,SO_MEML , ST_SKIP
-     ADD,    ALU_ADD,   SB_REG,         1,  SR_ALUL,      0,      0,         0,SO_MEML , ST_SKIP
-     SUB,    ALU_SUB,   SB_REG,         1,  SR_ALUL,      0,      0,         0,SO_MEML , ST_SKIP
-     AND,    ALU_AND,   SB_REG,         1,  SR_ALUL,      0,      0,         0,SO_MEML , ST_SKIP
-      OR,     ALU_OR,   SB_REG,         1,  SR_ALUL,      0,      0,         0,SO_MEML , ST_SKIP
-     XOR,    ALU_XOR,   SB_REG,         1,  SR_ALUL,      0,      0,         0,SO_MEML , ST_SKIP
-     MUL,    ALU_MUL,   SB_REG,         1,  SR_ALUL,      0,      0,         0,SO_MEML , ST_SKIP
-     DIV,    ALU_DIV,   SB_REG,         1,  SR_ALUL,      0,      0,         0,SO_MEML , ST_SKIP
-      BR,   ALU_NONE,  SB_NONE,         0,  SR_NONE,      0,      0,         2,SO_MEML , ST_SKIP
-     SLL,     ALU_SL,   SB_REG,         1,  SR_ALUL,      0,      0,         0,SO_MEML , ST_SKIP
-     SRL,     ALU_SR,   SB_REG,         1,  SR_ALUL,      0,      0,         0,SO_MEML , ST_SKIP
-     SRA,     ALU_RA,   SB_REG,         1,  SR_ALUL,      0,      0,         0,SO_MEML , ST_SKIP
-    SRAS,    ALU_RAS,   SB_REG,         1,  SR_ALUL,      0,      0,         0,SO_MEML , ST_SKIP
-    LWHI,   ALU_NONE,  SB_NONE,         1,  SR_MEMH,      1,      0,         3,SO_MEML , ST_SKIP
-    SWHI,   ALU_NONE,  SB_NONE,         0,  SR_NONE,      0,      0,         0,SO_MEMH , ST_SKIP
-    LWLO,   ALU_NONE,  SB_NONE,         1,  SR_MEML,      1,      0,         3,SO_MEML , ST_SKIP
-    SWLO,   ALU_NONE,  SB_NONE,         0,  SR_NONE,      0,      1,         3,SO_MEML , ST_SKIP
-     INC,    ALU_ADD,     SB_1,         1,  SR_ALUL,      0,      0,         0,SO_MEML , ST_SKIP
-     DEC,    ALU_SUB,     SB_1,         1,  SR_ALUL,      0,      0,         0,SO_MEML , ST_SKIP
-   GETAH,   ALU_NONE,  SB_NONE,         1,  SR_ALUH,      0,      0,         0,SO_MEML , ST_SKIP
-   GETIF,   ALU_NONE,  SB_NONE,         1,  SR_INTR,      0,      0,         0,SO_MEML , ST_SKIP
-    PUSH,   ALU_NONE,  SB_NONE,         0,  SR_NONE,      0,      1,         0,SO_MEML ,  ST_SUB
-     POP,   ALU_NONE,  SB_NONE,         1,  SR_MEML,      1,      0,         0,SO_MEML ,  ST_ADD
-     COM,   ALU_NONE,  SB_NONE,         1,   SR_COM,      0,      0,         1, SO_COM , ST_SKIP
-    CALL,   ALU_NONE,  SB_NONE,         0,  SR_NONE,      0,      0,         2,SO_MEML , ST_SKIP
-     RET,   ALU_NONE,  SB_NONE,         0,  SR_NONE,      0,      0,         0,SO_MEML , ST_SKIP
-    JUMP,   ALU_NONE,  SB_NONE,         0,  SR_NONE,      0,      0,         2,SO_MEML , ST_SKIP
-    RETI,   ALU_NONE,  SB_NONE,         0,  SR_NONE,      0,      0,         0,SO_MEML , ST_SKIP
-     CLC,   ALU_NONE,  SB_NONE,         0,  SR_NONE,      0,      0,         0,SO_MEML , ST_SKIP
-    SETC,   ALU_NONE,  SB_NONE,         0,  SR_NONE,      0,      0,         0,SO_MEML , ST_SKIP
-     CLS,   ALU_NONE,  SB_NONE,         0,  SR_NONE,      0,      0,         0,SO_MEML , ST_SKIP
-    SETS,   ALU_NONE,  SB_NONE,         0,  SR_NONE,      0,      0,         0,SO_MEML , ST_SKIP
-   SSETS,   ALU_NONE,  SB_NONE,         0,  SR_NONE,      0,      0,         0,SO_MEML , ST_SKIP
-     CLN,   ALU_NONE,  SB_NONE,         0,  SR_NONE,      0,      0,         0,SO_MEML , ST_SKIP
-    SETN,   ALU_NONE,  SB_NONE,         0,  SR_NONE,      0,      0,         0,SO_MEML , ST_SKIP
-   SSETN,   ALU_NONE,  SB_NONE,         0,  SR_NONE,      0,      0,         0,SO_MEML , ST_SKIP
-   RJUMP,   ALU_NONE,  SB_NONE,         0,  SR_NONE,      0,      0,         2,SO_MEML , ST_SKIP
-    RBWI,   ALU_NONE,  SB_NONE,         0,  SR_NONE,      0,      0,         1,SO_MEML , ST_SKIP
- default,   ALU_NONE,  SB_NONE,         0,  SR_NONE,      0,      0,         0,SO_MEML , ST_SKIP
+   instr, cdi.alu_op, cdi.selb, cdi.rw_en, cdi.selr, mem_rd, mem_wr, cdi.isize,cdi.selo ,cdi.stackop,cdi.pcop 
+    CPY0,   ALU_NONE,   SB_IMM,         1,   SR_IMM,      0,      0,         1,SO_MEML , ST_SKIP, PC_NONE 
+    CPY1,   ALU_NONE,   SB_IMM,         1,   SR_IMM,      0,      0,         1,SO_MEML , ST_SKIP, PC_NONE 
+    CPY2,   ALU_NONE,   SB_IMM,         1,   SR_IMM,      0,      0,         1,SO_MEML , ST_SKIP, PC_NONE 
+    CPY3,   ALU_NONE,   SB_IMM,         1,   SR_IMM,      0,      0,         1,SO_MEML , ST_SKIP, PC_NONE 
+    MOVE,   ALU_NONE,  SB_NONE,         1,   SR_REG,      0,      0,         0,SO_MEML , ST_SKIP, PC_NONE 
+     ADD,    ALU_ADD,   SB_REG,         1,  SR_ALUL,      0,      0,         0,SO_MEML , ST_SKIP, PC_NONE 
+     SUB,    ALU_SUB,   SB_REG,         1,  SR_ALUL,      0,      0,         0,SO_MEML , ST_SKIP, PC_NONE 
+     AND,    ALU_AND,   SB_REG,         1,  SR_ALUL,      0,      0,         0,SO_MEML , ST_SKIP, PC_NONE 
+      OR,     ALU_OR,   SB_REG,         1,  SR_ALUL,      0,      0,         0,SO_MEML , ST_SKIP, PC_NONE 
+     XOR,    ALU_XOR,   SB_REG,         1,  SR_ALUL,      0,      0,         0,SO_MEML , ST_SKIP, PC_NONE 
+     MUL,    ALU_MUL,   SB_REG,         1,  SR_ALUL,      0,      0,         0,SO_MEML , ST_SKIP, PC_NONE 
+     DIV,    ALU_DIV,   SB_REG,         1,  SR_ALUL,      0,      0,         0,SO_MEML , ST_SKIP, PC_NONE 
+      BR,   ALU_NONE,  SB_NONE,         0,  SR_NONE,      0,      0,         2,SO_MEML , ST_SKIP, PC_NONE 
+     SLL,     ALU_SL,   SB_REG,         1,  SR_ALUL,      0,      0,         0,SO_MEML , ST_SKIP, PC_NONE 
+     SRL,     ALU_SR,   SB_REG,         1,  SR_ALUL,      0,      0,         0,SO_MEML , ST_SKIP, PC_NONE 
+     SRA,     ALU_RA,   SB_REG,         1,  SR_ALUL,      0,      0,         0,SO_MEML , ST_SKIP, PC_NONE 
+    SRAS,    ALU_RAS,   SB_REG,         1,  SR_ALUL,      0,      0,         0,SO_MEML , ST_SKIP, PC_NONE 
+    LWHI,   ALU_NONE,  SB_NONE,         1,  SR_MEMH,      1,      0,         3,SO_MEML , ST_SKIP, PC_NONE 
+    SWHI,   ALU_NONE,  SB_NONE,         0,  SR_NONE,      0,      0,         0,SO_MEMH , ST_SKIP, PC_NONE 
+    LWLO,   ALU_NONE,  SB_NONE,         1,  SR_MEML,      1,      0,         3,SO_MEML , ST_SKIP, PC_NONE 
+    SWLO,   ALU_NONE,  SB_NONE,         0,  SR_NONE,      0,      1,         3,SO_MEML , ST_SKIP, PC_NONE 
+     INC,    ALU_ADD,     SB_1,         1,  SR_ALUL,      0,      0,         0,SO_MEML , ST_SKIP, PC_NONE 
+     DEC,    ALU_SUB,     SB_1,         1,  SR_ALUL,      0,      0,         0,SO_MEML , ST_SKIP, PC_NONE 
+   GETAH,   ALU_NONE,  SB_NONE,         1,  SR_ALUH,      0,      0,         0,SO_MEML , ST_SKIP, PC_NONE 
+   GETIF,   ALU_NONE,  SB_NONE,         1,  SR_INTR,      0,      0,         0,SO_MEML , ST_SKIP, PC_NONE 
+    PUSH,   ALU_NONE,  SB_NONE,         0,  SR_NONE,      0,      1,         0,SO_MEML ,  ST_SUB, PC_NONE 
+     POP,   ALU_NONE,  SB_NONE,         1,  SR_MEML,      1,      0,         0,SO_MEML ,  ST_ADD, PC_NONE 
+     COM,   ALU_NONE,  SB_NONE,         1,   SR_COM,      0,      0,         1, SO_COM , ST_SKIP, PC_NONE 
+    CALL,   ALU_NONE,  SB_NONE,         0,  SR_NONE,      0,      1,         0,SO_MEML ,  ST_SUB, PC_CALL 
+     RET,   ALU_NONE,  SB_NONE,         0,  SR_NONE,      1,      0,         2,SO_MEML ,  ST_ADD,  PC_RET 
+    JUMP,   ALU_NONE,  SB_NONE,         0,  SR_NONE,      0,      0,         0,SO_MEML , ST_NONE, PC_JUMP 
+    RETI,   ALU_NONE,  SB_NONE,         0,  SR_NONE,      1,      0,         2,SO_MEML ,  ST_SUB,  PC_RET 
+     CLC,   ALU_NONE,  SB_NONE,         0,  SR_NONE,      0,      0,         0,SO_MEML , ST_SKIP, PC_NONE 
+    SETC,   ALU_NONE,  SB_NONE,         0,  SR_NONE,      0,      0,         0,SO_MEML , ST_SKIP, PC_NONE 
+     CLS,   ALU_NONE,  SB_NONE,         0,  SR_NONE,      0,      0,         0,SO_MEML , ST_SKIP, PC_NONE 
+    SETS,   ALU_NONE,  SB_NONE,         0,  SR_NONE,      0,      0,         0,SO_MEML , ST_SKIP, PC_NONE 
+   SSETS,   ALU_NONE,  SB_NONE,         0,  SR_NONE,      0,      0,         0,SO_MEML , ST_SKIP, PC_NONE 
+     CLN,   ALU_NONE,  SB_NONE,         0,  SR_NONE,      0,      0,         0,SO_MEML , ST_SKIP, PC_NONE 
+    SETN,   ALU_NONE,  SB_NONE,         0,  SR_NONE,      0,      0,         0,SO_MEML , ST_SKIP, PC_NONE 
+   SSETN,   ALU_NONE,  SB_NONE,         0,  SR_NONE,      0,      0,         0,SO_MEML , ST_SKIP, PC_NONE 
+   RJUMP,   ALU_NONE,  SB_NONE,         0,  SR_NONE,      0,      0,         2,SO_MEML , ST_SKIP, PC_NONE 
+    RBWI,   ALU_NONE,  SB_NONE,         0,  SR_NONE,      0,      0,         1,SO_MEML , ST_SKIP, PC_NONE 
+ default,   ALU_NONE,  SB_NONE,         0,  SR_NONE,      0,      0,         0,SO_MEML , ST_SKIP, PC_NONE 

src/risc/controller.sv

@@ -30,6 +30,7 @@ module controller8(
             cdi.isize   = 1;
             cdi.selo    = SO_MEML;
             cdi.stackop = ST_SKIP;
+            cdi.pcop    = PC_NONE;
             `ifdef ADDOP
             op = CPY0;
             `endif
@@ -44,6 +45,7 @@ module controller8(
             cdi.isize   = 1;
             cdi.selo    = SO_MEML;
             cdi.stackop = ST_SKIP;
+            cdi.pcop    = PC_NONE;
             `ifdef ADDOP
             op = CPY1;
             `endif
@@ -58,6 +60,7 @@ module controller8(
             cdi.isize   = 1;
             cdi.selo    = SO_MEML;
             cdi.stackop = ST_SKIP;
+            cdi.pcop    = PC_NONE;
             `ifdef ADDOP
             op = CPY2;
             `endif
@@ -72,6 +75,7 @@ module controller8(
             cdi.isize   = 1;
             cdi.selo    = SO_MEML;
             cdi.stackop = ST_SKIP;
+            cdi.pcop    = PC_NONE;
             `ifdef ADDOP
             op = CPY3;
             `endif
@@ -86,6 +90,7 @@ module controller8(
             cdi.isize   = 0;
             cdi.selo    = SO_MEML;
             cdi.stackop = ST_SKIP;
+            cdi.pcop    = PC_NONE;
             `ifdef ADDOP
             op = MOVE;
             `endif
@@ -100,6 +105,7 @@ module controller8(
             cdi.isize   = 0;
             cdi.selo    = SO_MEML;
             cdi.stackop = ST_SKIP;
+            cdi.pcop    = PC_NONE;
             `ifdef ADDOP
             op = ADD;
             `endif
@@ -114,6 +120,7 @@ module controller8(
             cdi.isize   = 0;
             cdi.selo    = SO_MEML;
             cdi.stackop = ST_SKIP;
+            cdi.pcop    = PC_NONE;
             `ifdef ADDOP
             op = SUB;
             `endif
@@ -128,6 +135,7 @@ module controller8(
             cdi.isize   = 0;
             cdi.selo    = SO_MEML;
             cdi.stackop = ST_SKIP;
+            cdi.pcop    = PC_NONE;
             `ifdef ADDOP
             op = AND;
             `endif
@@ -142,6 +150,7 @@ module controller8(
             cdi.isize   = 0;
             cdi.selo    = SO_MEML;
             cdi.stackop = ST_SKIP;
+            cdi.pcop    = PC_NONE;
             `ifdef ADDOP
             op = OR;
             `endif
@@ -156,6 +165,7 @@ module controller8(
             cdi.isize   = 0;
             cdi.selo    = SO_MEML;
             cdi.stackop = ST_SKIP;
+            cdi.pcop    = PC_NONE;
             `ifdef ADDOP
             op = XOR;
             `endif
@@ -170,6 +180,7 @@ module controller8(
             cdi.isize   = 0;
             cdi.selo    = SO_MEML;
             cdi.stackop = ST_SKIP;
+            cdi.pcop    = PC_NONE;
             `ifdef ADDOP
             op = MUL;
             `endif
@@ -184,6 +195,7 @@ module controller8(
             cdi.isize   = 0;
             cdi.selo    = SO_MEML;
             cdi.stackop = ST_SKIP;
+            cdi.pcop    = PC_NONE;
             `ifdef ADDOP
             op = DIV;
             `endif
@@ -198,6 +210,7 @@ module controller8(
             cdi.isize   = 2;
             cdi.selo    = SO_MEML;
             cdi.stackop = ST_SKIP;
+            cdi.pcop    = PC_NONE;
             `ifdef ADDOP
             op = BR;
             `endif
@@ -212,6 +225,7 @@ module controller8(
             cdi.isize   = 0;
             cdi.selo    = SO_MEML;
             cdi.stackop = ST_SKIP;
+            cdi.pcop    = PC_NONE;
             `ifdef ADDOP
             op = SLL;
             `endif
@@ -226,6 +240,7 @@ module controller8(
             cdi.isize   = 0;
             cdi.selo    = SO_MEML;
             cdi.stackop = ST_SKIP;
+            cdi.pcop    = PC_NONE;
             `ifdef ADDOP
             op = SRL;
             `endif
@@ -240,6 +255,7 @@ module controller8(
             cdi.isize   = 0;
             cdi.selo    = SO_MEML;
             cdi.stackop = ST_SKIP;
+            cdi.pcop    = PC_NONE;
             `ifdef ADDOP
             op = SRA;
             `endif
@@ -254,6 +270,7 @@ module controller8(
             cdi.isize   = 0;
             cdi.selo    = SO_MEML;
             cdi.stackop = ST_SKIP;
+            cdi.pcop    = PC_NONE;
             `ifdef ADDOP
             op = SRAS;
             `endif
@@ -268,6 +285,7 @@ module controller8(
             cdi.isize   = 3;
             cdi.selo    = SO_MEML;
             cdi.stackop = ST_SKIP;
+            cdi.pcop    = PC_NONE;
             `ifdef ADDOP
             op = LWHI;
             `endif
@@ -282,6 +300,7 @@ module controller8(
             cdi.isize   = 0;
             cdi.selo    = SO_MEMH;
             cdi.stackop = ST_SKIP;
+            cdi.pcop    = PC_NONE;
             `ifdef ADDOP
             op = SWHI;
             `endif
@@ -296,6 +315,7 @@ module controller8(
             cdi.isize   = 3;
             cdi.selo    = SO_MEML;
             cdi.stackop = ST_SKIP;
+            cdi.pcop    = PC_NONE;
             `ifdef ADDOP
             op = LWLO;
             `endif
@@ -310,6 +330,7 @@ module controller8(
             cdi.isize   = 3;
             cdi.selo    = SO_MEML;
             cdi.stackop = ST_SKIP;
+            cdi.pcop    = PC_NONE;
             `ifdef ADDOP
             op = SWLO;
             `endif
@@ -324,6 +345,7 @@ module controller8(
             cdi.isize   = 0;
             cdi.selo    = SO_MEML;
             cdi.stackop = ST_SKIP;
+            cdi.pcop    = PC_NONE;
             `ifdef ADDOP
             op = INC;
             `endif
@@ -338,6 +360,7 @@ module controller8(
             cdi.isize   = 0;
             cdi.selo    = SO_MEML;
             cdi.stackop = ST_SKIP;
+            cdi.pcop    = PC_NONE;
             `ifdef ADDOP
             op = DEC;
             `endif
@@ -352,6 +375,7 @@ module controller8(
             cdi.isize   = 0;
             cdi.selo    = SO_MEML;
             cdi.stackop = ST_SKIP;
+            cdi.pcop    = PC_NONE;
             `ifdef ADDOP
             op = GETAH;
             `endif
@@ -366,6 +390,7 @@ module controller8(
             cdi.isize   = 0;
             cdi.selo    = SO_MEML;
             cdi.stackop = ST_SKIP;
+            cdi.pcop    = PC_NONE;
             `ifdef ADDOP
             op = GETIF;
             `endif
@@ -380,6 +405,7 @@ module controller8(
             cdi.isize   = 0;
             cdi.selo    = SO_MEML;
             cdi.stackop = ST_SUB;
+            cdi.pcop    = PC_NONE;
             `ifdef ADDOP
             op = PUSH;
             `endif
@@ -394,6 +420,7 @@ module controller8(
             cdi.isize   = 0;
             cdi.selo    = SO_MEML;
             cdi.stackop = ST_ADD;
+            cdi.pcop    = PC_NONE;
             `ifdef ADDOP
             op = POP;
             `endif
@@ -408,6 +435,7 @@ module controller8(
             cdi.isize   = 1;
             cdi.selo    = SO_COM;
             cdi.stackop = ST_SKIP;
+            cdi.pcop    = PC_NONE;
             `ifdef ADDOP
             op = COM;
             `endif
@@ -418,10 +446,11 @@ module controller8(
             cdi.rw_en   = 0;
             cdi.selr    = SR_NONE;
             mem_rd      = 0;
-            mem_wr      = 0;
-            cdi.isize   = 2;
+            mem_wr      = 1;
+            cdi.isize   = 0;
             cdi.selo    = SO_MEML;
-            cdi.stackop = ST_SKIP;
+            cdi.stackop = ST_SUB;
+            cdi.pcop    = PC_CALL;
             `ifdef ADDOP
             op = CALL;
             `endif
@@ -431,11 +460,12 @@ module controller8(
             cdi.selb    = SB_NONE;
             cdi.rw_en   = 0;
             cdi.selr    = SR_NONE;
-            mem_rd      = 0;
+            mem_rd      = 1;
             mem_wr      = 0;
-            cdi.isize   = 0;
+            cdi.isize   = 2;
             cdi.selo    = SO_MEML;
-            cdi.stackop = ST_SKIP;
+            cdi.stackop = ST_ADD;
+            cdi.pcop    = PC_RET;
             `ifdef ADDOP
             op = RET;
             `endif
@@ -447,9 +477,10 @@ module controller8(
             cdi.selr    = SR_NONE;
             mem_rd      = 0;
             mem_wr      = 0;
-            cdi.isize   = 2;
+            cdi.isize   = 0;
             cdi.selo    = SO_MEML;
-            cdi.stackop = ST_SKIP;
+            cdi.stackop = ST_NONE;
+            cdi.pcop    = PC_JUMP;
             `ifdef ADDOP
             op = JUMP;
             `endif
@@ -459,11 +490,12 @@ module controller8(
             cdi.selb    = SB_NONE;
             cdi.rw_en   = 0;
             cdi.selr    = SR_NONE;
-            mem_rd      = 0;
+            mem_rd      = 1;
             mem_wr      = 0;
-            cdi.isize   = 0;
+            cdi.isize   = 2;
             cdi.selo    = SO_MEML;
-            cdi.stackop = ST_SKIP;
+            cdi.stackop = ST_SUB;
+            cdi.pcop    = PC_RET;
             `ifdef ADDOP
             op = RETI;
             `endif
@@ -478,6 +510,7 @@ module controller8(
             cdi.isize   = 0;
             cdi.selo    = SO_MEML;
             cdi.stackop = ST_SKIP;
+            cdi.pcop    = PC_NONE;
             `ifdef ADDOP
             op = CLC;
             `endif
@@ -492,6 +525,7 @@ module controller8(
             cdi.isize   = 0;
             cdi.selo    = SO_MEML;
             cdi.stackop = ST_SKIP;
+            cdi.pcop    = PC_NONE;
             `ifdef ADDOP
             op = SETC;
             `endif
@@ -506,6 +540,7 @@ module controller8(
             cdi.isize   = 0;
             cdi.selo    = SO_MEML;
             cdi.stackop = ST_SKIP;
+            cdi.pcop    = PC_NONE;
             `ifdef ADDOP
             op = CLS;
             `endif
@@ -520,6 +555,7 @@ module controller8(
             cdi.isize   = 0;
             cdi.selo    = SO_MEML;
             cdi.stackop = ST_SKIP;
+            cdi.pcop    = PC_NONE;
             `ifdef ADDOP
             op = SETS;
             `endif
@@ -534,6 +570,7 @@ module controller8(
             cdi.isize   = 0;
             cdi.selo    = SO_MEML;
             cdi.stackop = ST_SKIP;
+            cdi.pcop    = PC_NONE;
             `ifdef ADDOP
             op = SSETS;
             `endif
@@ -548,6 +585,7 @@ module controller8(
             cdi.isize   = 0;
             cdi.selo    = SO_MEML;
             cdi.stackop = ST_SKIP;
+            cdi.pcop    = PC_NONE;
             `ifdef ADDOP
             op = CLN;
             `endif
@@ -562,6 +600,7 @@ module controller8(
             cdi.isize   = 0;
             cdi.selo    = SO_MEML;
             cdi.stackop = ST_SKIP;
+            cdi.pcop    = PC_NONE;
             `ifdef ADDOP
             op = SETN;
             `endif
@@ -576,6 +615,7 @@ module controller8(
             cdi.isize   = 0;
             cdi.selo    = SO_MEML;
             cdi.stackop = ST_SKIP;
+            cdi.pcop    = PC_NONE;
             `ifdef ADDOP
             op = SSETN;
             `endif
@@ -590,6 +630,7 @@ module controller8(
             cdi.isize   = 2;
             cdi.selo    = SO_MEML;
             cdi.stackop = ST_SKIP;
+            cdi.pcop    = PC_NONE;
             `ifdef ADDOP
             op = RJUMP;
             `endif
@@ -604,6 +645,7 @@ module controller8(
             cdi.isize   = 1;
             cdi.selo    = SO_MEML;
             cdi.stackop = ST_SKIP;
+            cdi.pcop    = PC_NONE;
             `ifdef ADDOP
             op = RBWI;
             `endif
@@ -618,6 +660,7 @@ module controller8(
             cdi.isize   = 0;
             cdi.selo    = SO_MEML;
             cdi.stackop = ST_SKIP;
+            cdi.pcop    = PC_NONE;
         end
     endcase
     end

src/risc/datapath.sv

@@ -57,7 +57,10 @@ module datapath8(
 		// TODO: missing overflow
 	);
 
-	// Program counter
+	// ======================== //
+	// 		Program Counter 	//
+	// ======================== //
+
 	logic bconst; // Use immediate to branch
 	word pc_off; // Program counter offset
 	reg [15:0] pcn, pca; // Program Counter Previous, to add
@@ -65,17 +68,25 @@ module datapath8(
 			if(rst) pc <= '0; 
 			else pc <= pcn;
 	end
-
-	assign bconst = 0;  // FIXME: temporary
-	assign pca = (bconst) ? imm[15:0] : pc;
-	assign pc_off = { 
+	
+	always_comb begin
+		bconst = 0;  // FIXME: temporary
+		case(cdi.pcop)
+			PC_NONE: pca = pc;
+			PC_CALL: pca = {imm[7:0], imm[15:8]};
+			PC_RET : pca = mem_rd;
+			PC_JUMP: pca = {imm[7:0], imm[15:8]};
+			default: pca = pc;
+		endcase
+		//pca = (bconst) ? {imm[7:0], imm[15:8]} : pc;
+		pc_off = { 
 			5'b0000_0, 
 			cdi.isize[0]&cdi.isize[1], 
 			cdi.isize[0]^cdi.isize[1], 
 			(~cdi.isize[1]&~cdi.isize[0])|(cdi.isize[1]&~cdi.isize[0])
-	}; // Adding 1 to 2bit value.
-	assign pcn = pca + pc_off;
-
+		}; // Adding 1 to 2bit value.
+		pcn = pca + pc_off;
+	end
 	
 	word interrupt_flag;
 	always_ff@(posedge clk) begin
@@ -88,22 +99,29 @@ module datapath8(
 	// 			Stack 			//
 	// ======================== //
 
-	logic [15:0] sp, sp_add, sp_next, sp_data;  // Stack pointer 
-	word st_lo, st_rd, st_wr;  // Stack data low byte reg
+	logic [15:0] sp, sp_add, sp_next, st_wr;  // Stack pointer 
+	word st_reg, st_rd;  // Stack data low byte reg
 	logic [23:0] sp_addr;
 	always_comb begin
-		sp_add = (cdi.stackop == ST_ADD) ? 'h0001 : 'hffff;
+		sp_add = (cdi.stackop == ST_ADD) ? 'h0002 : 'hfffe;
 		sp_next = sp + sp_add;
 		sp_addr = {9'b1111_1111_1, (cdi.stackop == ST_ADD) ? sp_next[15:1] : sp[15:1]};
-		st_rd = (sp[0]) ? mem_rd[7:0] : mem_rd[15:8];
-		st_wr = (sp[0]) ? r1 : st_lo;
+		st_rd = {mem_rd[7:0]};
+		st_wr = (cdi.pcop == PC_CALL) ? pc : {8'h00, r1};
+		//if(sp[0]) begin
+			//st_wr = {'h00, r1};
+			//st_rd = {mem_rd[7:0]};
+		//end else begin
+			//st_wr = {st_reg, r1};
+			//st_rd = {mem_rd[15:8]};
+		//end
 	end
 	
 	always_ff@(posedge clk) begin
 			if(rst)	sp <= 'hffff;
 			else begin
 				if(cdi.stackop != ST_SKIP) sp <= sp_next;
-				if(sp[0]) st_lo <= r1; 
+				if(sp[0]) st_reg <= r1; 
 			end
 	end
 
@@ -116,9 +134,8 @@ module datapath8(
 			if(rst) mem_wr_hi <= '0; 
 			else if(cdi.selo == SO_MEMH) mem_wr_hi <= r1;
 	end
-
-	assign mem_wr[7:0] = r1;
-	assign mem_wr[15:8] = (cdi.stackop == ST_SUB) ? st_wr : mem_wr_hi;
+	
+	assign mem_wr = (cdi.stackop == ST_SUB) ? st_wr : {mem_wr_hi, r1};
 	assign mem_addr = (cdi.stackop != ST_SKIP) ? sp_addr : imm;
 
 	// COM Write

src/risc/general.sv

@@ -100,12 +100,21 @@ package risc8_pkg;
 	} e_reg_addr;
 
 	typedef enum logic [1:0] {
+		ST_NONE= 2'bxx,
 		ST_SKIP= 2'b00,
 		ST_ADD = 2'b01,
 		ST_SUB = 2'b10,
 		ST_3   = 2'b11
 	} e_stackop;
 
+	typedef enum logic [2:0] {
+		PC_NONE= 3'b000,
+		PC_CALL= 3'b001,
+		PC_RET = 3'b010,
+		PC_RETI= 3'b011,
+		PC_JUMP= 3'b100
+	} e_pcop;
+
 endpackage
 
 interface risc8_cdi;  // Control Datapath interface	
@@ -118,6 +127,7 @@ interface risc8_cdi;  // Control Datapath interface
 	e_selb selb;
 	e_selo selo;
 	e_stackop stackop;
+	e_pcop pcop;
 	logic [2:0] alu_comp;
 	
 	// Register
@@ -127,13 +137,13 @@ interface risc8_cdi;  // Control Datapath interface
 	logic [1:0] isize; // instruction size between 1 and 4
 	
 	modport datapath(
-		input alu_op, selb, sign, alu_not, selo, stackop,
+		input alu_op, selb, sign, alu_not, selo, stackop, pcop,
 		output alu_comp,
 		input a1, a2, a3, rw_en, selr, mem_h, isize
 	);
 	
 	modport control(
-		output alu_op, selb, sign, alu_not, selo, stackop,
+		output alu_op, selb, sign, alu_not, selo, stackop, pcop,
 		input alu_comp,
 		output a1, a2, a3, rw_en, selr, mem_h, isize
 	);