Final report WIP

docs/final_report/6-results.tex

@@ -64,6 +64,31 @@ Other logic includes instruction decoding with ROM, register file, program count
 
 Much higher logic components in RISC can be also explained more complicated register file, ROM memory logic and program counter. All of these components has some additional logic for timing correction or additional functionality required by these blocks integration into datapath.
 
+\subsection{Power analysis}
+
+Power analysis was performed to analyse power consumption of both processors.
+This has been accomplished by connecting FPGA board to a laboratory power supply with 4V to an external power input. A shunt resistor of was used of 1.020$\Omega$ was connected in series to calculate current. Supply voltage and voltage across shut resistor were measured using oscilloscope with data sampling feature. Multiple tests have been performed with different processor configurations. Between each tests a period of about 5 minutes was given for FPGA to reach steady state. 
+
+
+\begin{colfigure}
+	\centering
+	\includegraphics[width=\linewidth]{../tests/power.eps}
+	\captionof{figure}{Measured power of processors when implemented on FPGA, running 16bit multiplication function in loop. None indicates auxiliary-only power.}
+	\label{fig:power}
+\end{colfigure}
+
+Figure \ref{fig:power} represents power results. Auxiliary power includes whole FPGA board, voltage regulators, and synthesised logic on FPGA required to support a processor (such as PLL, UART, Input/Output control, RAM). RISC and OISC bars in the graph indicate auxiliary power plus processor power, which means that the processor itself takes relatively small amount comparing to auxiliary power, about 0.5\%.
+
+During this test clock frequency of 1MHz was used. Due to equipment unavailability, further tests were not carried out to investigate power consumption at different frequencies. 
+
+\subsubsection{Activity Factor}
+An activity factor could be also found using Equation \ref{eq:activity_factor} where $P$ is power, $C_{total}$ indicate total gate capacitance and $V_{DD}$ indicate voltage supplied to the transistors.
+\begin{align}\label{eq:activity_factor}
+\alpha = \frac{P}{C_{total}\cdot f \cdot V_{DD}^2}
+\end{align}
+As $C_{total}$ and $V_{DD}$ are constants, measuring power at different frequencies allows finding activity factor. This value could be used to compare how much of a processor circuit is active. Further design improvements could be used to optimise power \autocite{8682289,7363689,1207041,6972455}.
+
+
 \subsection{Benchmark Programs}
 
 \colorbox{yellow}{\parbox{\columnwidth}{Description of each function in benchmark to be added.}}
@@ -204,6 +229,34 @@ Figure \ref{fig:program_size} represents effective program size for each test fu
 \end{colfigure}
 
 \subsection{Maximum clock frequency}
-\colorbox{yellow}{Description to be added.}
+To find maximum clock frequency, processors were loaded with basic print string function an d 16bit multiplication. Then frequency was constantly increased until resulting output though UART was not correct. 
+
+In order to change clock frequency, three parameters were changed and HDL code resynthesised: 
+\begin{description}
+	\item[$\bullet$ PLL frequency multiplier and divider:]
+	PLL takes 50MHz clock that is sourced from crystal on FPGA board and converts it to master clock $f_{mclk}$. Multiplier and divider values are used to adjust $f_{mclk}$.
+	
+	\item[$\bullet$ UART frequency divider:]
+	Division value was calculated as $D = \left \lfloor \frac{f_{mclk}}{4 f_{baud}} \right \rfloor$. UART rate was set to 9600 baud. UART module itself has four times oversample. 
+\end{description}
+Frequency was changed in 5MHz increments. 
+
+Theoretical maximum frequency was found using Quartus Timing Analysis tool. Slow 1200mV 85$^{\circ}$C model was used. 
 
+\begin{center}
+	\begin{tabular}{ l | c | c  }
+		     & Theoretical & Actual \\ \hline
+		RISC & 114.08MHz & 75-70MHz \\ \hline
+		OISC & 64.68MHz & 45-40MHz \\
+	\end{tabular}
+	\captionof{table}{Theoretical and actual maximum frequencies of both processors.}
+	\label{tab:max_freq}
+\end{center}
+
+Theoretical and actual results show unexpected results shown in Table \ref{tab:max_freq}, RISC operated at about 40\% higher maximum frequency than OISC.
+
+As explained in Subsection \ref{subsec:oisc_cell_issue}, OISC logic blocks has about twice less time for data propagation. Keeping that in mind, and assuming that latch propagation and register setup periods are insignificant to critical path of OISC logic block, maximum OISC frequency could be double as high as, reaching 80-90MHz. This also assumes that there is no other part of processor would have limit. Further timing analysis needs to be carried out to confirm this.
+
+\subsection{Future work}
+\colorbox{yellow}{Description to be added.}
 

docs/final_report/index.toc

@@ -44,56 +44,64 @@
 \defcounter {refsection}{0}\relax 
 \contentsline {subsubsection}{\numberline {4.2.2}OISC Datapath}{9}{subsubsection.4.2.2}% 
 \defcounter {refsection}{0}\relax 
+\contentsline {subsubsection}{\numberline {4.2.3}OISC Datapath Implementation Problems}{9}{subsubsection.4.2.3}% 
+\defcounter {refsection}{0}\relax 
 \contentsline {subsection}{\numberline {4.3}Stack}{9}{subsection.4.3}% 
 \defcounter {refsection}{0}\relax 
 \contentsline {subsubsection}{\numberline {4.3.1}RISC Stack}{9}{subsubsection.4.3.1}% 
 \defcounter {refsection}{0}\relax 
-\contentsline {subsubsection}{\numberline {4.3.2}OISC Stack}{9}{subsubsection.4.3.2}% 
+\contentsline {subsubsection}{\numberline {4.3.2}OISC Stack}{10}{subsubsection.4.3.2}% 
+\defcounter {refsection}{0}\relax 
+\contentsline {subsection}{\numberline {4.4}Program Counters}{10}{subsection.4.4}% 
+\defcounter {refsection}{0}\relax 
+\contentsline {subsubsection}{\numberline {4.4.1}RISC Program Counter}{10}{subsubsection.4.4.1}% 
+\defcounter {refsection}{0}\relax 
+\contentsline {subsubsection}{\numberline {4.4.2}OISC Program Counter}{11}{subsubsection.4.4.2}% 
 \defcounter {refsection}{0}\relax 
-\contentsline {subsection}{\numberline {4.4}Program Counter}{9}{subsection.4.4}% 
+\contentsline {subsection}{\numberline {4.5}Arithmetic Logic Unit}{12}{subsection.4.5}% 
 \defcounter {refsection}{0}\relax 
-\contentsline {subsubsection}{\numberline {4.4.1}RISC PC}{9}{subsubsection.4.4.1}% 
+\contentsline {subsubsection}{\numberline {4.5.1}OISC ALU}{12}{subsubsection.4.5.1}% 
 \defcounter {refsection}{0}\relax 
-\contentsline {subsubsection}{\numberline {4.4.2}OISC PC}{9}{subsubsection.4.4.2}% 
+\contentsline {subsubsection}{\numberline {4.5.2}RISC ALU}{12}{subsubsection.4.5.2}% 
 \defcounter {refsection}{0}\relax 
-\contentsline {subsection}{\numberline {4.5}Arithmetic Logic Unit}{9}{subsection.4.5}% 
+\contentsline {subsection}{\numberline {4.6}Program Memory}{13}{subsection.4.6}% 
 \defcounter {refsection}{0}\relax 
-\contentsline {subsubsection}{\numberline {4.5.1}OISC ALU}{10}{subsubsection.4.5.1}% 
+\contentsline {subsubsection}{\numberline {4.6.1}RISC Program Memory}{13}{subsubsection.4.6.1}% 
 \defcounter {refsection}{0}\relax 
-\contentsline {subsubsection}{\numberline {4.5.2}RISC ALU}{11}{subsubsection.4.5.2}% 
+\contentsline {subsubsection}{\numberline {4.6.2}OISC Program Memory}{13}{subsubsection.4.6.2}% 
 \defcounter {refsection}{0}\relax 
-\contentsline {subsection}{\numberline {4.6}Program Memory}{11}{subsection.4.6}% 
+\contentsline {subsection}{\numberline {4.7}Instruction decoding}{14}{subsection.4.7}% 
 \defcounter {refsection}{0}\relax 
-\contentsline {subsubsection}{\numberline {4.6.1}RISC Program Memory}{11}{subsubsection.4.6.1}% 
+\contentsline {subsubsection}{\numberline {4.7.1}RISC}{14}{subsubsection.4.7.1}% 
 \defcounter {refsection}{0}\relax 
-\contentsline {subsubsection}{\numberline {4.6.2}OISC Program Memory}{12}{subsubsection.4.6.2}% 
+\contentsline {subsubsection}{\numberline {4.7.2}OISC}{14}{subsubsection.4.7.2}% 
 \defcounter {refsection}{0}\relax 
-\contentsline {subsection}{\numberline {4.7}Instruction decoding}{12}{subsection.4.7}% 
+\contentsline {subsection}{\numberline {4.8}Assembly}{15}{subsection.4.8}% 
 \defcounter {refsection}{0}\relax 
-\contentsline {subsubsection}{\numberline {4.7.1}RISC}{12}{subsubsection.4.7.1}% 
+\contentsline {subsection}{\numberline {4.9}System setup}{17}{subsection.4.9}% 
 \defcounter {refsection}{0}\relax 
-\contentsline {subsubsection}{\numberline {4.7.2}OISC}{13}{subsubsection.4.7.2}% 
+\contentsline {section}{\numberline {5}Results and Analysis}{17}{section.5}% 
 \defcounter {refsection}{0}\relax 
-\contentsline {subsection}{\numberline {4.8}Assembly}{13}{subsection.4.8}% 
+\contentsline {subsection}{\numberline {5.1}FPGA logic component composition}{17}{subsection.5.1}% 
 \defcounter {refsection}{0}\relax 
-\contentsline {subsection}{\numberline {4.9}System setup}{15}{subsection.4.9}% 
+\contentsline {subsection}{\numberline {5.2}Power analysis}{18}{subsection.5.2}% 
 \defcounter {refsection}{0}\relax 
-\contentsline {section}{\numberline {5}Results and Analysis}{16}{section.5}% 
+\contentsline {subsubsection}{\numberline {5.2.1}Activity Factor}{19}{subsubsection.5.2.1}% 
 \defcounter {refsection}{0}\relax 
-\contentsline {subsection}{\numberline {5.1}FPGA logic component composition}{16}{subsection.5.1}% 
+\contentsline {subsection}{\numberline {5.3}Benchmark Programs}{19}{subsection.5.3}% 
 \defcounter {refsection}{0}\relax 
-\contentsline {subsection}{\numberline {5.2}Benchmark Programs}{17}{subsection.5.2}% 
+\contentsline {subsubsection}{\numberline {5.3.1}Performance}{19}{subsubsection.5.3.1}% 
 \defcounter {refsection}{0}\relax 
-\contentsline {subsubsection}{\numberline {5.2.1}Performance}{17}{subsubsection.5.2.1}% 
+\contentsline {subsubsection}{\numberline {5.3.2}Instruction composition}{19}{subsubsection.5.3.2}% 
 \defcounter {refsection}{0}\relax 
-\contentsline {subsubsection}{\numberline {5.2.2}Instruction composition}{17}{subsubsection.5.2.2}% 
+\contentsline {subsubsection}{\numberline {5.3.3}Program space}{20}{subsubsection.5.3.3}% 
 \defcounter {refsection}{0}\relax 
-\contentsline {subsubsection}{\numberline {5.2.3}Program space}{18}{subsubsection.5.2.3}% 
+\contentsline {subsection}{\numberline {5.4}Maximum clock frequency}{22}{subsection.5.4}% 
 \defcounter {refsection}{0}\relax 
-\contentsline {subsection}{\numberline {5.3}Maximum clock frequency}{19}{subsection.5.3}% 
+\contentsline {subsection}{\numberline {5.5}Future work}{22}{subsection.5.5}% 
 \defcounter {refsection}{0}\relax 
-\contentsline {section}{\numberline {6}Conclusion}{19}{section.6}% 
+\contentsline {section}{\numberline {6}Conclusion}{22}{section.6}% 
 \defcounter {refsection}{0}\relax 
-\contentsline {section}{\numberline {7}Appendix}{22}{section.7}% 
+\contentsline {section}{\numberline {7}Appendix}{25}{section.7}% 
 \defcounter {refsection}{0}\relax 
-\contentsline {subsection}{\numberline {7.1}Processor instruction set tables}{22}{subsection.7.1}% 
+\contentsline {subsection}{\numberline {7.1}Processor instruction set tables}{25}{subsection.7.1}%