Final project WIP

docs/final_report/3-objectives.tex

@@ -1,4 +1,4 @@
-\iffalse
+\iffalse
 This chapter describes your Goals and Objectives. 
 Indicate how your work is intended to expand on previous historical work.
 Present your motivations; why are you doing this?
@@ -10,3 +10,32 @@ These types of projects involve the design and construction of some
 electrical or electronic apparatus or device within the bounds 
 of the department's educational mandate.
 \fi
+
+
+This is just a list of research papers and relative context:
+
+
+\autocite{5403730} - TTA instruction redundancy remoal method with base plus offset addressing load/store function unit (LSFU)
+\autocite{4627144} - TTA code compression using arithmetic coding
+\autocite{5936440} - Novel processor for Multiple Instruction Multiple Data packet triggered architecture for pipeline and parallel processing.
+\autocite{1213033} - Another template based compression method to improve code density
+
+
+\autocite{1511285} - Scalable FIR filtering on TTA
+\autocite{289981} - MOVE32INT TTA implementation. Achieved parallel processing with 80MHz 320Mops/s comparing to RISC 20MHz 20Mops/s. Includes automated design
+\autocite{6855236} - Parallel programming of a TTA for LDPC encoding application
+\autocite{922340} - TTA for encryption specific ASIP
+\autocite{4595596} - Focuses on software pipelining and solved with GNU Linear Programming Kit (Very interesting)
+\autocite{1207041} - Try to reduce power by encoding buses thus reducing switching (read a bit more)
+\autocite{6972455} - Reducing VLIW interconnects to achieve 10\% core energy in 4-issue VLIW
+\autocite{7363689} - Implementing TTA for SDR and focuses on power optimisations. It show ~24.8-26.1\% decrease in power consumption with 3.3\% area increase.
+\autocite{8425389} - Using soft cores in comparision to VLIW to have 67\% of resources with up to 88\% improvement in execution time and 21-49\% cost in program size.
+\autocite{8682289} - Low power implementation TTA for FFT
+\autocite{8573494} - Compressive Sensing Applications on ARM Cortex-A15, NIOS II and TTA architectures. TTA has lowest time and power consumption, however about 2.5 higher area to NIOS II
+
+\autocite{6128530} - Implemented TTA that is efficent on RSA calculations, 3 1024bit pairs/s at 100MHz
+\autocite{1540373} - ASIP TTA for matrix inversion.
+\autocite{840031}  - Introduce Test space exploration costs for TTA templates.
+\autocite{6403142} - A novel microachitecture that combines VLIW and TTA for different applications. Takes less area than existing TTA and VLIW
+\autocite{6893206} - Instruction template based compression method for TTA processors
+

docs/final_report/4-theory.tex

@@ -7,9 +7,12 @@ What mathematical bases must be understood in order to interpret your results in
 Give the reader a solid understanding of the foundations here.
 \fi
 
+RISC that this paper will be exploring is classical SISO (single instruction, single operation) processor. TTAs are usually of type SIMT (single instruction, multiple transports) \autocite{289981}; A middle between these two classes is SIMO type (single instruction, multiple operation)
 
 \textbf{Decided design criteria:}
 \begin{description}
 	\item[$\bullet$] Minimal instruction size
 	\item[$\bullet$] Minimalistic design
-\end{description}
+\end{description}
+
+%There are many papers looking into application specific TTAs. 

docs/final_report/8-appendix.tex

@@ -4,7 +4,7 @@
 \arrayrulecolor{black}
 \begin{longtable}[h!]{| l | p{.70\textwidth} | c |}
 \caption{Instruction set for RISC processor. * Required immediate size in bytes}
-\label{table:risc_instructions}\\
+\label{tab:risc_instructions}\\
 
 \hline
 \rowcolor[rgb]{0.82,0.82,0.82}

docs/final_report/index.tex

@@ -1,46 +1,45 @@
-\documentclass[a4paper,12pt]{article}
+\documentclass[a4paper,12pt,twocolumn]{article}
 \usepackage[top=1in,bottom=1in,left=1in,right=1in]{geometry}
 \usepackage[T1]{fontenc}
 \usepackage[utf8]{inputenc}
-\usepackage{newunicodechar}
-\usepackage{lmodern}
-\usepackage{textgreek}
+%\usepackage{newunicodechar}
+%\usepackage{lmodern}
+%\usepackage{textgreek}
 \usepackage{amsmath}
 \usepackage{mathtools}
 \usepackage{graphicx}
-\usepackage{pdflscape}
-\usepackage{svg}
+\usepackage{float}
 \usepackage{caption}
-\usepackage{enumitem}
+\usepackage{enumitem}
 \usepackage{lipsum}
 \usepackage{listings}
-
+\usepackage{balance}
 
 
 \usepackage{tabularx}
-\usepackage{blindtext}
+%\usepackage{blindtext}
 \usepackage{hyperref}
-\usepackage{pgfgantt}
-\usepackage{colortbl}
-\usepackage{pdfpages}
+%\usepackage{pgfgantt}
 \usepackage{setspace}
 \usepackage{subcaption}
 \usepackage{tikz}
 \usepackage{chngcntr}
 \usepackage{longtable}
 \usepackage{xcolor,colortbl}
-\usepackage{pdfpages}
-\counterwithin{figure}{subsection}
 \usepackage{multicol} 
-\usepackage{mdframed} 
+%\usepackage{mdframed} 
 \usepackage{oubraces}
+\usepackage{stfloats}
+%\usepackage{fixltx2e}
 
 \setcounter{tocdepth}{3}
-
+\counterwithin{figure}{subsection}
+\counterwithin{table}{subsection}
 
 \usepackage[backend=bibtex]{biblatex}
 \addbibresource{references.bib}
 
+% Our base colours
 \definecolor{c1}{HTML}{ff7568} 
 \definecolor{c2}{HTML}{8cbfff} 
 \definecolor{c3}{HTML}{a6ddb7} 
@@ -55,6 +54,16 @@
 \lstset{language=asm, basicstyle=\ttfamily, commentstyle=\color{gray}, emphstyle={\color{darkred}}}
 
 
+% This enviroment ensures that structures like listing and tables are not broken between columns or pages.
+\newenvironment{blockpage}
+{\begin{center}\begin{minipage}[c]{\linewidth}}
+{\end{minipage}\end{center}}
+
+% This allows placing figure in column
+\newenvironment{colfigure}
+{\par\medskip\noindent\minipage{\linewidth}}
+{\endminipage\par\medskip}
+
 \begin{document}
 	
 	\begin{titlepage}
@@ -103,8 +112,6 @@
 	\end{titlepage}
 	
 	\pagebreak
-	
-	\begin{multicols}{2}
 	\section{Abstract}\label{sec:abstract}
 	\input{1-abstract.tex}
 	\section{Introduction}\label{sec:introduction}
@@ -121,8 +128,8 @@
 	\input{7-conclusion.tex}
 	\section{References}
 	\printbibliography
-	\end{multicols}
 	\pagebreak
+	\onecolumn
 	\section{Appendix}\label{sec:appendix}
 	\input{8-appendix.tex}
 	

docs/final_report/references.bib

@@ -1,4 +1,49 @@
-@article{beldianu_ziavras_2014,
+@INPROCEEDINGS{5403730,  
+	author={ {Su Wang} and  {Suying Yao} and  {Wei Guo} and  {Jizeng Wei}},  
+	booktitle={Proceedings of the 2009 12th International Symposium on Integrated Circuits},  
+	title={An instruction redundancy removal method on a transport triggered architecture processor},   
+	year={2009},  volume={},  number={},  pages={602-604}
+},
+
+@INPROCEEDINGS{6855236,  author={B. {Rister} and P. {Jääskeläinen} and O. {Silvén} and J. {Hannuksela} and J. R. {Cavallaro}},  booktitle={2014 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP)},  title={Parallel programming of a symmetric transport-triggered architecture with applications in flexible LDPC encoding},   year={2014},  volume={},  number={},  pages={8380-8384},}
+
+@INPROCEEDINGS{922340,  author={P. {Hamalainen} and M. {Hannikainen} and T. {Hamalainen} and H. {Corporaal} and J. {Saarvinen}},  booktitle={ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196)},  title={Implementation of encryption algorithms on transport triggered architectures},   year={2001},  volume={4},  number={},  pages={726-729 vol. 4},}
+
+@INPROCEEDINGS{4595596,  author={L. {Jiang} and Y. {Zhu} and Y. {Wei}},  booktitle={2008 International Conference on Embedded Software and Systems},  title={Software Pipelining with Minimal Loop Overhead on Transport Triggered Architecture},   year={2008},  volume={},  number={},  pages={451-458},}
+
+@INPROCEEDINGS{1207041,  author={T. {Pionteck} and A. {Garcia} and L. D. {Kabulepa} and M. {Glesner}},  booktitle={14th IEEE International Workshop on Rapid Systems Prototyping, 2003. Proceedings.},  title={Hardware evaluation of low power communication mechanisms for transport-triggered architectures},   year={2003},  volume={},  number={},  pages={141-147},}
+
+@INPROCEEDINGS{6972455,  author={T. {Viitanen} and H. {Kultala} and P. {Jääskeläinen} and J. {Takala}},  booktitle={2014 International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES)},  title={Heuristics for greedy transport triggered architecture interconnect exploration},   year={2014},  volume={},  number={},  pages={1-7},}
+
+@INPROCEEDINGS{7363689,  author={J. {Multanen} and T. {Viitanen} and H. {Linjamäki} and H. {Kultala} and P. {Jääskeläinen} and J. {Takala} and L. {Koskinen} and J. {Simonsson} and H. {Berg} and K. {Raiskila} and T. {Zetterman}},  booktitle={2015 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS)},  title={Power optimizations for transport triggered SIMD processors},   year={2015},  volume={},  number={},  pages={303-309},}
+
+@INPROCEEDINGS{8425389,  author={P. {Jääskeläinen} and A. {Tervo} and G. {Payá Vayá} and T. {Viitanen} and N. {Behmann} and J. {Takala} and H. {Blume}},  booktitle={2018 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)},  title={Transport-Triggered Soft Cores},   year={2018},  volume={},  number={},  pages={83-90},}
+
+@INPROCEEDINGS{8682289,  author={J. {Žádník} and J. {Takala}},  booktitle={ICASSP 2019 - 2019 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP)},  title={Low-power Programmable Processor for Fast Fourier Transform Based on Transport Triggered Architecture},   year={2019},  volume={},  number={},  pages={1423-1427},}
+
+@INPROCEEDINGS{8573494,  author={M. {Safarpour} and I. {Hautala} and O. {Silvén}},  booktitle={2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)},  title={An Embedded Programmable Processor for Compressive Sensing Applications},   year={2018},  volume={},  number={},  pages={1-5},}
+
+@INPROCEEDINGS{4627144,  author={J. {Wei} and W. {Guo} and J. {Sun} and Y. {Yao}},  booktitle={2008 International Conference on Embedded Software and Systems Symposia},  title={Program Compression Based on Arithmetic Coding on Transport Triggered Architecture},   year={2008},  volume={},  number={},  pages={126-131},}
+
+@INPROCEEDINGS{5936440,  author={F. {Adamec} and T. {Fryza}},  booktitle={Proceedings of 21st International Conference Radioelektronika 2011},  title={Introduction to the new Packet Triggered Architecture for pipelined and parallel data processing},   year={2011},  volume={},  number={},  pages={1-4},}
+
+@INPROCEEDINGS{1213033,  author={J. {Heikkinen} and T. {Rantanen} and A. {Cilio} and J. {Takala} and H. {Corporaal}},  booktitle={The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, 2003. Proceedings.},  title={Evaluating template-based instruction compression on transport triggered architectures},   year={2003},  volume={},  number={},  pages={192-195},}
+
+@INPROCEEDINGS{1511285,  author={P. {Salmela} and T. {Jarvinen} and J. {Takala} and T. {Sipila}},  booktitle={International Symposium on Signals, Circuits and Systems, 2005. ISSCS 2005.},  title={Scalable FIR filtering on transport triggered architecture processor},   year={2005},  volume={2},  number={},  pages={493-496 Vol. 2},}
+
+@INPROCEEDINGS{289981,  author={H. {Corporaal}},  booktitle={Proceedings of 4th Great Lakes Symposium on VLSI},  title={Design of transport triggered architectures},   year={1994},  volume={},  number={},  pages={130-135},}
+
+@INPROCEEDINGS{6128530,  author={J. {Hu} and W. {Guo} and J. {Wei} and Y. {Chang} and D. {Sun}},  booktitle={2011 Fourth International Symposium on Parallel Architectures, Algorithms and Programming},  title={A Novel Architecture for Fast RSA Key Generation Based on RNS},   year={2011},  volume={},  number={},  pages={345-349},}
+
+@INPROCEEDINGS{840031,  author={V. A. {Zivkovic} and R. J. W. T. {Tangelder} and H. G. {Kerkhoff}},  booktitle={Proceedings Design, Automation and Test in Europe Conference and Exhibition 2000 (Cat. No. PR00537)},  title={Design and test space exploration of transport-triggered architectures},   year={2000},  volume={},  number={},  pages={146-151},}
+
+@INPROCEEDINGS{1540373,  author={A. {Burian} and P. {Salmela} and J. {Takala}},  booktitle={2005 IEEE International Conference on Application-Specific Systems, Architecture Processors (ASAP'05)},  title={Complex fixed-point matrix inversion using transport triggered architecture},   year={2005},  volume={},  number={},  pages={107-112},}
+
+@INPROCEEDINGS{6403142,  author={S. {Hauser} and N. {Moser} and B. {Juurlink}},  booktitle={NORCHIP 2012},  title={SynZEN: A hybrid TTA/VLIW architecture with a distributed register file},   year={2012},  volume={},  number={},  pages={1-4},}
+
+@INPROCEEDINGS{6893206,  author={J. {Helkala} and T. {Viitanen} and H. {Kultala} and P. {Jääskeläinen} and J. {Takala} and T. {Zetterman} and H. {Berg}},  booktitle={2014 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV)},  title={Variable length instruction compression on Transport Triggered Architectures},   year={2014},  volume={},  number={},  pages={149-155},}
+
+@INPROCEEDINGS{beldianu_ziavras_2014,
 	title={ASIC Design of Shared Vector Accelerators for Multicore Processors},
 	DOI={10.1109/sbac-pad.2014.13},
 	journal={2014 IEEE 26th International Symposium on Computer Architecture and High Performance Computing},
@@ -6,7 +51,7 @@
 	year={2014}
 },
 
-@article{dharshana_balasubramanian_arun_2016,
+@INPROCEEDINGS{dharshana_balasubramanian_arun_2016,
 	title={Encrypted computation on a one instruction set architecture},
 	DOI={10.1109/iccpct.2016.7530376},
 	journal={2016 International Conference on Circuit, Power and Computing Technologies (ICCPCT)},
@@ -14,7 +59,7 @@
 	year={2016}
 },
 
-@article{ong_ang_seng_2010,
+@INPROCEEDINGS{ong_ang_seng_2010,
 	title={Implementation of (15, 9) Reed Solomon Minimal Instruction Set Computing on FPGA using Handel-C},
 	DOI={10.1109/iccaie.2010.5735103},
 	journal={2010 International Conference on Computer Applications and Industrial Electronics},
@@ -22,7 +67,7 @@
 	year={2010}
 },
 
-@article{yokota_saso_hara-azumi_2017,
+@INPROCEEDINGS{yokota_saso_hara-azumi_2017,
 	title={One-instruction set computer-based multicore processors for energy-efficient streaming data processing},
 	DOI={10.1145/3130265.3130318},
 	journal={Proceedings of the 28th International Symposium on Rapid System Prototyping Shortening the Path from Specification to Prototype - RSP '17},
@@ -30,7 +75,7 @@
 	year={2017}
 }
 
-@article{ahmed_sakamoto_anderson_hara-azumi_2015,
+@INPROCEEDINGS{ahmed_sakamoto_anderson_hara-azumi_2015,
 	title={Synthesizable-from-C Embedded Processor Based on MIPS-ISA and OISC},
 	DOI={10.1109/euc.2015.23},
 	journal={2015 IEEE 13th International Conference on Embedded and Ubiquitous Computing},
@@ -38,7 +83,7 @@
 	year={2015}
 },
 
-@article{blem_menon_sankaralingam_2013,
+@INPROCEEDINGS{blem_menon_sankaralingam_2013,
 	title={Power struggles: Revisiting the RISC vs. CISC debate on contemporary ARM and x86 architectures},
 	DOI={10.1109/hpca.2013.6522302},
 	journal={2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA)},
@@ -63,7 +108,7 @@
 	year={2013}
 },
 
-@article{jamil_1995,
+@INPROCEEDINGS{jamil_1995,
 	title={RISC versus CISC},
 	volume={14},
 	DOI={10.1109/45.464688},
@@ -74,7 +119,7 @@
 	pages={13-16}
 },
 
-@article{kong_ang_seng_adejo_2010,
+@INPROCEEDINGS{kong_ang_seng_adejo_2010,
 	title={Minimal Instruction Set FPGA AES processor using Handel},
 	DOI={10.1109/iccaie.2010.5735100},
 	journal={2010 International Conference on Computer Applications and Industrial Electronics},
@@ -82,7 +127,7 @@
 	year={2010}
 }
 
-@article{morain_1989,
+@INPROCEEDINGS{morain_1989,
 title={Atkin's Test: News from the Front},
 DOI={10.1007/3-540-46885-4_59},
 journal={Lecture Notes in Computer Science},