Working prototyte

UCL_project_y3.qsf

@@ -69,19 +69,15 @@ set_location_assignment PIN_B9 -to switches[2]
 set_location_assignment PIN_M15 -to switches[3]
 set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
 set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation
-set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH testbench_1 -section_id eda_simulation
+set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH risc_test -section_id eda_simulation
 set_global_assignment -name EDA_TEST_BENCH_NAME testbench_1 -section_id eda_simulation
 set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id testbench_1
 set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME testbench_1 -section_id testbench_1
 set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
 set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
 set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
-set_global_assignment -name EDA_TEST_BENCH_FILE src/blocks/reg_file_tb.sv -section_id testbench_1
-set_global_assignment -name EDA_TEST_BENCH_FILE src/blocks/memory.sv -section_id testbench_1
-set_global_assignment -name EDA_TEST_BENCH_FILE src/blocks/alu.sv -section_id testbench_1
-set_global_assignment -name EDA_TEST_BENCH_FILE src/controller.sv -section_id testbench_1
-set_global_assignment -name EDA_TEST_BENCH_FILE src/datapath.sv -section_id testbench_1
-set_global_assignment -name EDA_TEST_BENCH_FILE src/cpu.sv -section_id testbench_1
+set_global_assignment -name SYSTEMVERILOG_FILE src/risc/alu.sv
+set_global_assignment -name SYSTEMVERILOG_FILE src/risc/risc.sv
 set_global_assignment -name MIF_FILE memory/rom_test.mem
 set_global_assignment -name SYSTEMVERILOG_FILE src/datapath.sv
 set_global_assignment -name SYSTEMVERILOG_FILE src/blocks/instr_mem.sv
@@ -92,4 +88,14 @@ set_global_assignment -name SYSTEMVERILOG_FILE src/blocks/alu.sv
 set_global_assignment -name SYSTEMVERILOG_FILE src/io_unit.sv
 set_global_assignment -name SYSTEMVERILOG_FILE src/general.sv
 set_global_assignment -name SYSTEMVERILOG_FILE src/controller.sv
+set_global_assignment -name EDA_TEST_BENCH_NAME risc_test -section_id eda_simulation
+set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id risc_test
+set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME risc_test -section_id risc_test
+set_global_assignment -name EDA_TEST_BENCH_FILE src/risc/alu.sv -section_id risc_test
+set_global_assignment -name EDA_TEST_BENCH_FILE src/blocks/reg_file_tb.sv -section_id testbench_1
+set_global_assignment -name EDA_TEST_BENCH_FILE src/blocks/memory.sv -section_id testbench_1
+set_global_assignment -name EDA_TEST_BENCH_FILE src/blocks/alu.sv -section_id testbench_1
+set_global_assignment -name EDA_TEST_BENCH_FILE src/controller.sv -section_id testbench_1
+set_global_assignment -name EDA_TEST_BENCH_FILE src/datapath.sv -section_id testbench_1
+set_global_assignment -name EDA_TEST_BENCH_FILE src/cpu.sv -section_id testbench_1
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

memory/rom_test.mem

@@ -4,9 +4,9 @@ FA // imm
 24 // ADDI regB = 01
 01 // imm
 31 // SUB regA = regA - regB
-00
-00
-00
+83 // SW mem[regC] = regA 
+60 // ~regA
+73 // LW regA = mem[regC]
 00
 00
 00

src/blocks/memory.sv

@@ -1,15 +1,15 @@
 import project_pkg::*;
 
-module memory(clk, addr, rd_data, wr_data, wr_en);	
-	input clk, wr_en;
-	input word addr;
-	input word wr_data;
-	output word rd_data;
+module memory(
+		input 	logic 	clk, we,
+		input 	word 	a, rd, 
+		output 	word 	wd
+	);	
 	
 	logic [word_size-1:0]memory[mem_size-1:0];
-	assign rd_data = memory[addr];
+	assign rd = memory[a];
 	
-	always_ff@(posedge clk) if(wr_en) memory[addr] <= wr_data;
+	always_ff@(posedge clk) if(we) memory[a] <= wd;
 	
 	
 endmodule

src/general.sv

@@ -1,7 +1,7 @@
 package project_pkg;
 		
 	localparam word_size = 8;
-	localparam mem_size = 256;
+	localparam mem_size = 8;
 	localparam rom_size = 256;
 	localparam reg_size = 4;
 
@@ -32,11 +32,10 @@ package project_pkg;
 		JEQ =4'hC,  // Jump to $imm if $rs == $rt
 		ZERO=4'hD,  // $rs = 0x00
 		__0 =4'hE,  //
-		__1 =4'hF   //
-		
+		__1 =4'hF   //		
 	} e_instr;
 	
-		typedef enum logic [2:0] { 
+	typedef enum logic [2:0] { 
 		ALU_ADD=3'b000,
 		ALU_SUB=3'b001,
 		ALU_AND=3'b010,

src/io_unit.sv

@@ -6,6 +6,10 @@ module io_unit(switches, keys, leds);
 	
 	assign rst = keys[0];
 	assign clk = keys[1];
-	cpu CPU(clk, rst);
-	
+	logic mem_wr;
+	word pc, instr, imm, mem_addr, mem_data, mem_rd_data;	
+	cpu CPU(clk, rst, instr, imm, pc, mem_addr, mem_wr, mem_data, mem_rd_data);
+	instr_mem #("/home/min/devel/fpga/ucl_project_y3/memory/rom_test.mem") IMEM(pc, instr, imm);	
+	memory RAM(clk, mem_addr, mem_data, mem_rd_data, mem_wr);	
+
 endmodule