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+# UCL 3rd year project
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+## Performance characterisation of 8-bit RISC and OISC architectures
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+The aim is to compare similar characteristic RISC and OISC architectures to determinate advantages and trade-offs following points:
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+* Which processor is easier to implement and expand;
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+* Which processor requires less resources to implement;
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+* Which processor performs on common benchmark;
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+Possible application of both architectures could be use inside of microcontroller or SoC (System on a chip) systems similar to 8bit Atmel AVR or Mirochip PIC microcontrollers, therefore processors must be capable of controlling and communicating with external modules such as UART\footnote{Universal asynchronous receiver-transmitter} and GPIO (General Purpose Input/Output).
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+
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+## Project Structure
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+This project based on Intel Quartus. Hardware is implemented in SystemVerilog.
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+Project directories:
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+* *src* - HDL files,
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+* *tools* - Implemented tools like compiler for designed architecture,
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+* *memory* - Instructions and machine code,
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+* *docs* - All documentation.
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