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@@ -1,7 +1,11 @@
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-QUARTUS_DIR = /opt/altera/18.1/quartus/bin
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+QUARTUS_DIR = /opt/altera/18.1/quartus
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+MODELSIM_DIR = /opt/altera/18.1/modelsim_ase
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PROJECT_NAME = UCL_project_y3
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-QUARTUS_MAP = ${QUARTUS_DIR}/quartus_map --read_settings_files=on --write_settings_files=off ${PROJECT_NAME} -c ${PROJECT_NAME}
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+QUARTUS_MAP = ${QUARTUS_DIR}/bin/quartus_map --read_settings_files=on --write_settings_files=off ${PROJECT_NAME} -c ${PROJECT_NAME}
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+MODELSIM_GUI = ${QUARTUS_DIR}/bin/quartus_sh -t "${QUARTUS_DIR}/common/tcl/internal/nativelink/qnativesim.tcl" --rtl_sim "${PROJECT_NAME}" "${PROJECT_NAME}"
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+MODELSIM_BIN = ${MODELSIM_DIR}/bin/vsim
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+
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# Genreate sv case table from csv
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GENSV = python3 tools/gen_sv.py
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@@ -16,6 +20,15 @@ analysis:
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synthesis:
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${QUARTUS_MAP}
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+modelsim_cli:
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+ ${MODELSIM_BIN} -c
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+
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+modelsim_gui:
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+ ${MODELSIM_GUI}
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+
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+compile:
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+ ${MODELSIM_BIN} -c -do simulation/modelsim/${PROJECT_NAME}_run_msim_rtl_verilog.do -do exit
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+
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gentable:
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$(foreach x,$(GENTABLE_CSV),$(call execute-gentable,./$(x)))
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