Cleanup

Moved risc components to dedicated directory

UCL_project_y3.qsf

@@ -85,16 +85,16 @@ set_global_assignment -name EDA_TEST_BENCH_FILE src/controller.sv -section_id te
 set_location_assignment PIN_R8 -to clk
 set_location_assignment PIN_D3 -to rx
 set_location_assignment PIN_C3 -to tx
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+set_global_assignment -name SYSTEMVERILOG_FILE src/risc/io_unit.sv
+set_global_assignment -name SYSTEMVERILOG_FILE src/risc/general.sv
+set_global_assignment -name SYSTEMVERILOG_FILE src/risc/datapath.sv
+set_global_assignment -name SYSTEMVERILOG_FILE src/risc/cpu.sv
+set_global_assignment -name SYSTEMVERILOG_FILE src/risc/controller.sv
+set_global_assignment -name MIF_FILE memory/rom_test.mem
 set_global_assignment -name SYSTEMVERILOG_FILE src/blocks/clk_div.sv
 set_global_assignment -name VERILOG_FILE src/blocks/uart.v
-set_global_assignment -name MIF_FILE memory/rom_test.mem
-set_global_assignment -name SYSTEMVERILOG_FILE src/datapath.sv
 set_global_assignment -name SYSTEMVERILOG_FILE src/blocks/instr_mem.sv
-set_global_assignment -name SYSTEMVERILOG_FILE src/cpu.sv
 set_global_assignment -name SYSTEMVERILOG_FILE src/blocks/reg_file.sv
 set_global_assignment -name SYSTEMVERILOG_FILE src/blocks/memory.sv
-set_global_assignment -name SYSTEMVERILOG_FILE src/blocks/alu.sv
-set_global_assignment -name SYSTEMVERILOG_FILE src/io_unit.sv
-set_global_assignment -name SYSTEMVERILOG_FILE src/general.sv
-set_global_assignment -name SYSTEMVERILOG_FILE src/controller.sv
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+set_global_assignment -name SYSTEMVERILOG_FILE src/blocks/alu.sv

src/cpu_block.bdf

@@ -1,590 +0,0 @@
-/*
-WARNING: Do NOT edit the input and output ports in this file in a text
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-/*
-Copyright (C) 2018  Intel Corporation. All rights reserved.
-Your use of Intel Corporation's design tools, logic functions 
-and other software and tools, and its AMPP partner logic 
-functions, and any output files from any of the foregoing 
-(including device programming or simulation files), and any 
-associated documentation or information are expressly subject 
-to the terms and conditions of the Intel Program License 
-Subscription Agreement, the Intel Quartus Prime License Agreement,
-the Intel FPGA IP License Agreement, or other applicable license
-agreement, including, without limitation, that your use is for
-the sole purpose of programming logic devices manufactured by
-Intel and sold by Intel or its authorized distributors.  Please
-refer to the applicable agreement for further details.
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