Implemented working control

Inclued a bunch of fixes that caused modelsim to not compile.

UCL_project_y3.qsf

@@ -59,12 +59,6 @@ set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH testbench_1 -se
 set_global_assignment -name EDA_TEST_BENCH_NAME testbench_1 -section_id eda_simulation
 set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id testbench_1
 set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME testbench_1 -section_id testbench_1
-set_global_assignment -name EDA_TEST_BENCH_FILE src/blocks/reg_file_tb.sv -section_id testbench_1
-set_global_assignment -name EDA_TEST_BENCH_FILE src/blocks/memory.sv -section_id testbench_1
-set_global_assignment -name EDA_TEST_BENCH_FILE src/blocks/alu.sv -section_id testbench_1
-set_global_assignment -name EDA_TEST_BENCH_FILE src/datapath.sv -section_id testbench_1
-set_global_assignment -name EDA_TEST_BENCH_FILE src/cpu.sv -section_id testbench_1
-set_global_assignment -name EDA_TEST_BENCH_FILE src/controller.sv -section_id testbench_1
 set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
 set_location_assignment PIN_P2 -to DRAM_ADDR[0]
 set_location_assignment PIN_L4 -to DRAM_ADDR[12]
@@ -142,4 +136,12 @@ set_global_assignment -name SYSTEMVERILOG_FILE src/blocks/reg_file.sv
 set_global_assignment -name SYSTEMVERILOG_FILE src/blocks/memory.sv
 set_global_assignment -name QIP_FILE quartus/pll_clk.qip
 set_global_assignment -name SYSTEMVERILOG_FILE src/blocks/alu.sv
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+set_global_assignment -name EDA_TEST_BENCH_FILE src/blocks/alu.sv -section_id testbench_1
+set_global_assignment -name EDA_TEST_BENCH_FILE src/blocks/instr_mem.sv -section_id testbench_1
+set_global_assignment -name EDA_TEST_BENCH_FILE src/blocks/memory.sv -section_id testbench_1
+set_global_assignment -name EDA_TEST_BENCH_FILE src/blocks/sdram_control.sv -section_id testbench_1
+set_global_assignment -name EDA_TEST_BENCH_FILE src/risc/general.sv -section_id testbench_1
+set_global_assignment -name EDA_TEST_BENCH_FILE src/risc/controller.sv -section_id testbench_1
+set_global_assignment -name EDA_TEST_BENCH_FILE src/risc/datapath.sv -section_id testbench_1
+set_global_assignment -name EDA_TEST_BENCH_FILE src/risc/cpu.sv -section_id testbench_1

simulation/modelsim/UCL_project_y3_run_msim_rtl_verilog.do

@@ -5,22 +5,20 @@ if {[file exists rtl_work]} {
 vlib rtl_work
 vmap work rtl_work
 
-vlog -sv -work work +incdir+/home/min/devel/fpga/ucl_project_y3/src {/home/min/devel/fpga/ucl_project_y3/src/general.sv}
-vlog -sv -work work +incdir+/home/min/devel/fpga/ucl_project_y3/src {/home/min/devel/fpga/ucl_project_y3/src/datapath.sv}
-vlog -sv -work work +incdir+/home/min/devel/fpga/ucl_project_y3/src/blocks {/home/min/devel/fpga/ucl_project_y3/src/blocks/instr_mem.sv}
-vlog -sv -work work +incdir+/home/min/devel/fpga/ucl_project_y3/src {/home/min/devel/fpga/ucl_project_y3/src/cpu.sv}
+vlog -sv -work work +incdir+/home/min/devel/fpga/ucl_project_y3/src/blocks {/home/min/devel/fpga/ucl_project_y3/src/blocks/fifo.v}
+vlog -sv -work work +incdir+/home/min/devel/fpga/ucl_project_y3/src/blocks {/home/min/devel/fpga/ucl_project_y3/src/blocks/uart.v}
+vlog -sv -work work +incdir+/home/min/devel/fpga/ucl_project_y3/quartus {/home/min/devel/fpga/ucl_project_y3/quartus/pll_clk.v}
+vlog -sv -work work +incdir+/home/min/devel/fpga/ucl_project_y3/db {/home/min/devel/fpga/ucl_project_y3/db/pll_clk_altpll.v}
+vlog -sv -work work +incdir+/home/min/devel/fpga/ucl_project_y3/src {/home/min/devel/fpga/ucl_project_y3/src/project.sv}
+vlog -sv -work work +incdir+/home/min/devel/fpga/ucl_project_y3/src/blocks {/home/min/devel/fpga/ucl_project_y3/src/blocks/sdram_control.sv}
 vlog -sv -work work +incdir+/home/min/devel/fpga/ucl_project_y3/src/blocks {/home/min/devel/fpga/ucl_project_y3/src/blocks/reg_file.sv}
-vlog -sv -work work +incdir+/home/min/devel/fpga/ucl_project_y3/src/blocks {/home/min/devel/fpga/ucl_project_y3/src/blocks/memory.sv}
+vlog -sv -work work +incdir+/home/min/devel/fpga/ucl_project_y3/src {/home/min/devel/fpga/ucl_project_y3/src/top.sv}
 vlog -sv -work work +incdir+/home/min/devel/fpga/ucl_project_y3/src/blocks {/home/min/devel/fpga/ucl_project_y3/src/blocks/alu.sv}
-vlog -sv -work work +incdir+/home/min/devel/fpga/ucl_project_y3/src {/home/min/devel/fpga/ucl_project_y3/src/io_unit.sv}
-vlog -sv -work work +incdir+/home/min/devel/fpga/ucl_project_y3/src {/home/min/devel/fpga/ucl_project_y3/src/controller.sv}
+vlog -sv -work work +incdir+/home/min/devel/fpga/ucl_project_y3/src/risc {/home/min/devel/fpga/ucl_project_y3/src/risc/general.sv}
+vlog -sv -work work +incdir+/home/min/devel/fpga/ucl_project_y3/src/risc {/home/min/devel/fpga/ucl_project_y3/src/risc/cpu.sv}
+vlog -sv -work work +incdir+/home/min/devel/fpga/ucl_project_y3/src/risc {/home/min/devel/fpga/ucl_project_y3/src/risc/datapath.sv}
+vlog -sv -work work +incdir+/home/min/devel/fpga/ucl_project_y3/src/risc {/home/min/devel/fpga/ucl_project_y3/src/risc/controller.sv}
 
-vlog -sv -work work +incdir+/home/min/devel/fpga/ucl_project_y3/src/blocks {/home/min/devel/fpga/ucl_project_y3/src/blocks/reg_file_tb.sv}
-vlog -sv -work work +incdir+/home/min/devel/fpga/ucl_project_y3/src/blocks {/home/min/devel/fpga/ucl_project_y3/src/blocks/memory.sv}
-vlog -sv -work work +incdir+/home/min/devel/fpga/ucl_project_y3/src/blocks {/home/min/devel/fpga/ucl_project_y3/src/blocks/alu.sv}
-vlog -sv -work work +incdir+/home/min/devel/fpga/ucl_project_y3/src {/home/min/devel/fpga/ucl_project_y3/src/datapath.sv}
-vlog -sv -work work +incdir+/home/min/devel/fpga/ucl_project_y3/src {/home/min/devel/fpga/ucl_project_y3/src/cpu.sv}
-vlog -sv -work work +incdir+/home/min/devel/fpga/ucl_project_y3/src {/home/min/devel/fpga/ucl_project_y3/src/controller.sv}
 
 vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs="+acc"  testbench_1
 

src/blocks/alu.sv

@@ -25,7 +25,7 @@ endpackage
 import alu_pkg::*;
 
 module alu(
-	a, b, r, r_high, op, cin, sign, zero, cout, gt, eq, overflow
+	a, b, r, r_high, op, cin, sign, zero, cout, gt, eq, overflow, r_high_en
 );
 	parameter WORD=8;
 	localparam WSIZE=$clog2(WORD);
@@ -34,7 +34,7 @@ module alu(
 	input logic 			cin, sign;
 	input logic [WORD-1:0] 	a, b;
 	
-	output logic 			zero, cout, gt, eq, overflow;
+	output logic 			zero, cout, gt, eq, overflow, r_high_en;
 	output logic [WORD-1:0] r, r_high;
 	
 	logic [WSIZE-1:0] shmt;
@@ -54,31 +54,42 @@ module alu(
 	// Overflow/Underflow flag	
 	logic [1:0] overLSB;
 	logic overFlag;
-	assign overLSB = {a[WORD-1], b[WORD-1], r[WORD-1]};	
+	//assign overLSB = {a[WORD-1:WORD-1], b[WORD-1:WORD-1], r[WORD-1:WORD-1]};	
 	assign overFlag = (overLSB == 3'b110 || overLSB == 3'b001) ? 1 : 0;
 	assign overflow = sign && arithmeticOp ? overFlag : 0;	
 	
 	// Carry out flag
-	assign cout = arithmeticOp && ~sign ? coutF : 0;	
+	logic cout0, cout1;
+	assign cout = (op == ALU_ADD || op == ALU_SUB) && ~sign ? coutF : 0;
+	assign coutF = (op == ALU_ADD) ? cout0 : cout1;
+
+	logic [WORD-1:0] radd, rsub, r_low;
+	logic [WORD*2-1:0] rmul, rdiv;
+	assign {radd,cout0} = a + b + cin;
+	assign {rsub,cout1} = a - b - cin;
+	assign rmul = a * b;
+	assign rdiv = {a/b,a%b};
+  	assign r_high = (op == ALU_MUL) ? rmul[15:8] : rdiv[15:8];
+	assign r_high_en = (op == ALU_MUL || op == ALU_DIV);
 
 	always_comb begin
 	case(op)
-		ALU_ADD: {r,cout} = a + b + cin;
-		ALU_SUB: {r,cout} = a - b - cin;
-		ALU_AND: r = a & b;
-		ALU_OR : r = a | b;
-		ALU_XOR: r = a ^ b;
+		ALU_ADD:  r = radd;
+		ALU_SUB:  r = rsub;
+		ALU_AND:  r = a & b;
+		ALU_OR :  r = a | b;
+		ALU_XOR:  r = a ^ b;
 		ALU_NAND: r = ~(a & b);
 		ALU_NOR : r = ~(a | b);
 		ALU_XNOR: r = ~(a ^ b);
-		ALU_SL: r = a << shmt;
-		ALU_SR: r = (sign) ? sr : a >> shmt;
-		ALU_RA: r = {a[0], a[WORD-1:1]};
-		ALU_RAS: r = {a[WORD-2:0], a[WORD-1]};
-		ALU_MUL: {r_high, r} = a * b;
-		ALU_DIV: {r, r_high} = {a / b, a % b};
-		ALU_MOD: r = a % b;
-		default: r = 0;
+		ALU_SL:   r = a << shmt;
+		ALU_SR:   r = (sign) ? sr : a >> shmt;
+		ALU_RA:   r = {a[0], a[WORD-1:1]};
+		ALU_RAS:  r = {a[WORD-2:0], a[WORD-1]};
+		ALU_MUL:  r = rmul[WORD*2-1:WORD];
+		ALU_DIV:  r = rdiv[WORD*2-1:WORD];
+		ALU_MOD:  r = rdiv[WORD-1:0];
+		default:  r = 0;
 	endcase
 	end
 

src/project.sv

@@ -23,23 +23,23 @@ endinterface
 module com_block(
 	input clk, rst,
 	// Communication to processor
-	input  [7:0]	addr,
-	input  [7:0]	in_data,
-	output [7:0]	out_data,
-	output 			interrupt,
+	input  wire [7:0]	addr,
+	input  reg  [7:0]	in_data,
+	output reg  [7:0]	out_data,
+	output wire			interrupt,
 
 	// IO
-	output [7:0]	leds,
-	input  [3:0]	switches,
-	output 			uart0_tx,
-	input 			uart0_rx,
-	input 			key1
+	output reg  [7:0]	leds,
+	input  wire  [3:0]	switches,
+	output wire			uart0_tx,
+	input  wire			uart0_rx,
+	input  wire			key1
 );
 
 	/* UART */
 	reg [2:0] uart0_reg;
 	reg uart0_transmit;
-	wire [7:0] tx_byte, rx_byte;
+	reg [7:0] tx_byte, rx_byte;
 	// Clock divide = 1e6 / (9600 * 4)
 	uart#(.CLOCK_DIVIDE(26)) uart0(
 			.clk(clk), 
@@ -55,23 +55,18 @@ module com_block(
 	);
 
 	always_ff@(posedge clk) begin
-	//	if(addr == 8'h06) leds <= in_data;
-	//end
+		if(addr == 8'h06) leds <= in_data;
+		if(addr == 8'h05) tx_byte <= in_data;
+		if(addr == 8'h05) uart0_transmit <= 1;
+		else uart0_transmit <= 0; 
+	end
 
-	//always_comb begin
+	always_comb begin
 	case(addr)
-			8'h04: out_data <= {5'b0, uart0_reg};
-			8'h05: begin
-				tx_byte <= in_data;
-				uart0_transmit <= 1;
-				out_data <= {5'b0, uart0_reg};
-			end
-			8'h07: out_data <= {4'b0, switches};
-			8'h08: leds <= in_data;
-			default: begin 
-				out_data <= 0;
-				uart0_transmit <= 0;
-			end
+			8'h04: out_data = {5'b0, uart0_reg};
+			8'h05: out_data = {5'b0, uart0_reg};
+			8'h07: out_data = {4'b0, switches};
+			default: out_data = 0;
 	endcase
 	end
 endmodule

src/risc/controller.csv

@@ -1,4 +1,4 @@
- instr_op, cdi.alu_op, cdi.selb, cdi.rw_en, cdi.selr, mem_rd, mem_wr
+ instr, cdi.alu_op, cdi.selb, cdi.rw_en, cdi.selr, mem_rd, mem_wr
      MOVE,   ALU_NONE,      SB_NONE,         1,     SR_COM,      0,      0
      CPY0,   ALU_NONE,       SB_IMM,         1,     SR_IMM,      0,      0
      CPY1,   ALU_NONE,       SB_IMM,         1,     SR_IMM,      0,      0

src/risc/controller.sv

@@ -4,17 +4,18 @@ import alu_pkg::*;
 module controller8(
 		input word instr,
 		risc8_cdi.control cdi,
-		output mem_wr, mem_rd	
+		output reg mem_wr, mem_rd	
 );
 	// Instruction decoding
-	assign instr_op 	= e_instr'(instr[7:4]);
 	assign cdi.a1		= e_reg_addr'(instr[3:2]);
 	assign cdi.a2		= e_reg_addr'(instr[1:0]);
 	assign cdi.a3 		= cdi.a1; // Assuming destination always first operand
+	
+	e_instr op;
 
 	// generated table
     always_comb begin
-    casez(instr_op)
+    casez(instr)
         MOVE   : begin
             cdi.alu_op = ALU_NONE;
             cdi.selb   = SB_NONE;
@@ -365,148 +366,26 @@ module controller8(
 
 endmodule
 
-//module controller(instr, zero, alu_op, alu_ex, mem_wr, reg_wr, 
-//		pc_src, rimm, alu_src, mem_to_reg, instr_op, rd, rs, sp_wr, mem_sp);
-//	input word instr;
-//	input logic zero; // That's from ALU for J instructions
-//	output e_alu_op alu_op;
-//	output e_alu_ext_op alu_ex;
-//	output logic mem_wr, reg_wr, rimm, mem_to_reg, pc_src, alu_src;
-//	output e_instr instr_op;
-//	output e_reg rs, rd;
-//	output logic sp_wr, mem_sp;
-//
-//	// Instruction decoding
-//	assign instr_op 	= e_instr'(instr[7:4]);
-//	assign rd 			= e_reg'(instr[3:2]);
-//	assign rs 			= e_reg'(instr[1:0]);
-//	
-//	e_alu_op alu_subsel;
-//	//assign alu_subsel = (instr_op == JEQ) ? ALU_SUB : ALU_CPY;
-//	assign alu_subsel = (instr_op == JEQ) ? ALU_SUB: ALU_ADD;
-//	assign alu_op = instr_op[3] ? alu_subsel : e_alu_op'(instr_op[2:0]);
-//	assign reg_wr = ~instr_op[3] | instr_op == LW | instr_op == POP; 
-//	
-//	assign mem_wr = instr_op == SW | instr_op == PUSH;
-//	assign mem_to_reg = instr_op == LW | instr_op == POP;
-//	assign pc_src = (zero && instr_op == JEQ) | instr_op == JMP;
-//	
-//	assign alu_src = (instr_op == CPY & rd == rs);	
-//	assign rimm = (alu_src) | instr_op == JEQ;	
-//	assign alu_ex = e_alu_ext_op'(rs);
-//
-//	// Stack instructions
-//	assign mem_sp = instr_op[0];
-//	assign sp_wr = instr_op == PUSH | instr_op == POP;
-//endmodule
-//
-//module controller_tb;
-//	word instr;
-//	logic zero, mem_wr, reg_wr, alu_src, mem_to_reg, pc_src;
-//	e_alu_op alu_op;
-//
-//	controller CTR(instr, zero, alu_op, mem_wr, reg_wr, pc_src, alu_src, mem_to_reg);
-//
-//	initial begin
-//		instr = 8'h00;
-//		zero = 1;
-//		#5ns;
-//		//assert(alu_op == ALU_NOP);
-//		assert(mem_wr == 0);
-//		assert(reg_wr == 0);
-//		assert(pc_src == 0);
-//		assert(alu_src == 0);
-//		assert(mem_to_reg == 0);
-//		instr = 8'h10;
-//		#5ns;
-//		assert(alu_op == ALU_ADD);
-//		assert(mem_wr == 0);
-//		assert(reg_wr == 1);
-//		assert(pc_src == 0);
-//		assert(alu_src == 0);
-//		assert(mem_to_reg == 0);
-//		instr = 8'h20;
-//		#5ns;
-//		assert(alu_op == ALU_ADD);
-//		assert(mem_wr == 0);
-//		assert(reg_wr == 1);
-//		assert(pc_src == 0);
-//		assert(alu_src == 1);
-//		assert(mem_to_reg == 0);
-//		instr = 8'h30;
-//		#5ns;
-//		assert(alu_op == ALU_SUB);
-//		assert(mem_wr == 0);
-//		assert(reg_wr == 1);
-//		assert(pc_src == 0);
-//		assert(alu_src == 0);
-//		assert(mem_to_reg == 0);
-//		instr = 8'h40;
-//		#5ns;
-//		assert(alu_op == ALU_AND);
-//		assert(mem_wr == 0);
-//		assert(reg_wr == 1);
-//		assert(pc_src == 0);
-//		assert(alu_src == 0);
-//		assert(mem_to_reg == 0);
-//		instr = 8'h50;
-//		#5ns;
-//		assert(alu_op == ALU_OR);
-//		assert(mem_wr == 0);
-//		assert(reg_wr == 1);
-//		assert(pc_src == 0);
-//		assert(alu_src == 0);
-//		assert(mem_to_reg == 0);
-//		instr = 8'h60;
-//		#5ns;
-//		//assert(alu_op == ALU_NOT);
-//		assert(mem_wr == 0);
-//		assert(reg_wr == 1);
-//		assert(pc_src == 0);
-//		assert(alu_src == 0);
-//		assert(mem_to_reg == 0);
-//		instr = 8'h70;
-//		#5ns;
-//		//assert(alu_op == ALU_NOP);
-//		assert(mem_wr == 0);
-//		assert(reg_wr == 1);
-//		assert(pc_src == 0);
-//		assert(alu_src == 0);
-//		assert(mem_to_reg == 1);
-//		instr = 8'h80;
-//		#5ns;
-//		//assert(alu_op == ALU_NOP);
-//		assert(mem_wr == 1);
-//		assert(reg_wr == 0);
-//		assert(pc_src == 0);
-//		assert(alu_src == 0);
-//		assert(mem_to_reg == 0);
-//		instr = 8'hB0;
-//		#5ns;
-//		//assert(alu_op == ALU_NOP);
-//		assert(mem_wr == 0);
-//		assert(reg_wr == 1);
-//		assert(pc_src == 0);
-//		assert(alu_src == 0);
-//		assert(mem_to_reg == 0);
-//		instr = 8'hC0;
-//		#5ns;
-//		assert(alu_op == ALU_SUB);
-//		assert(mem_wr == 0);
-//		assert(reg_wr == 0);
-//		assert(pc_src == 1);
-//		assert(alu_src == 0);
-//		assert(mem_to_reg == 0);
-//		zero = 0;
-//		#5ns;
-//		assert(alu_op == ALU_SUB);
-//		assert(mem_wr == 0);
-//		assert(reg_wr == 0);
-//		assert(pc_src == 0);
-//		assert(alu_src == 0);
-//		assert(mem_to_reg == 0);
-//
-//		$stop;
-//	end
-//endmodule
+`timescale 1ns / 1ns
+module controller8_tb;
+	word instr;
+	risc8_cdi cdi();
+	logic mem_wr, mem_rd;
+	controller8 c0(instr, cdi, mem_wr, mem_rd);
+
+	initial begin
+		instr = 8'b0000_0000;
+		cdi.alu_comp = 3'b000;
+		#10ns;
+		instr = 8'b0000_0100;
+		#10ns;
+		instr = 8'b0001_0001;
+		#10ns;
+		instr = 8'b0010_0001;
+		#10ns;
+		instr = 8'b1111_1111;
+		#10ns;
+	end
+
+endmodule
 

src/risc/cpu.sv

@@ -1,4 +1,3 @@
-`timescale 1ns / 100ps
 import risc8_pkg::*;
 import alu_pkg::*;
 
@@ -50,6 +49,7 @@ module risc8_cpu(processor_port port);
 
 endmodule
 
+`timescale 1ns / 1ns
 module risc8_cpu_tb;
 	logic clk, rst, mem_wr; 
 	word pc, instr, imm, mem_addr, mem_data, mem_rd_data;	

src/risc/general.sv

@@ -1,33 +1,3 @@
-import alu_pkg::*;
-
-interface risc8_cdi;  // Control Datapath interface
-	
-	// ALU
-	e_alu_op alu_op;
-	logic sign, alu_not;
-	e_selb selb;
-	logic [2:0] alu_comp;
-	
-	// Register
-	reg_addr a1, a2, a3;
-	logic rw_en, mem_h;
-	e_selr selr;
-	
-	modport datapath(
-		input alu_op, selb, sign, alu_not,
-		output alu_comp,
-		input a1, a2, a3, rw_en, selr, mem_h
-	);
-	
-	modport control(
-		output alu_op, selb, sign, alu_not,
-		input alu_comp,
-		output a1, a2, a3, rw_en, selr, mem_h
-	);
-
-endinterface
-
-
 package risc8_pkg;
 
 	localparam word_size = 8;
@@ -220,3 +190,34 @@ package risc8x_pkg;
 	} e_instr;
 
 endpackage
+
+
+interface risc8_cdi;  // Control Datapath interface	
+	import risc8_pkg::*;
+	import alu_pkg::*;
+
+	// ALU
+	e_alu_op alu_op;
+	logic sign, alu_not;
+	e_selb selb;
+	logic [2:0] alu_comp;
+	
+	// Register
+	reg_addr a1, a2, a3;
+	logic rw_en, mem_h;
+	e_selr selr;
+	
+	modport datapath(
+		input alu_op, selb, sign, alu_not,
+		output alu_comp,
+		input a1, a2, a3, rw_en, selr, mem_h
+	);
+	
+	modport control(
+		output alu_op, selb, sign, alu_not,
+		input alu_comp,
+		output a1, a2, a3, rw_en, selr, mem_h
+	);
+
+endinterface
+

src/top.sv

@@ -76,6 +76,23 @@ module top(
 		.DRAM_BA(DRAM_BA)	
 	);
 
+	//Communication block
+	wire [7:0] com0_addr, com0_wr, com0_rd;
+	wire com0_interrupt;
+
+	com_block com0 (
+		.clk(mclk),
+		.rst(rst),
+		.addr(com0_addr),
+		.in_data(com0_wr),
+		.out_data(com0_rd),
+		.interrupt(com0_interrupt),
+		.leds(LED),
+		.switches(SWITCH),
+		.uart0_rx(RX),
+		.uart0_tx(TX),
+		.key1(~KEY[1])
+	);
 
 	// Processor
 	processor_port port0 (
@@ -97,23 +114,5 @@ module top(
 
 	risc8_cpu cpu_block0(port0);
 
-	//Communication block
-	wire [7:0] com0_addr, com0_wr, com0_rd;
-	wire com0_interrupt;
-
-	com_block com0 (
-		.clk(mclk),
-		.rst(rst),
-		.addr(com0_addr),
-		.in_data(com0_wr),
-		.out_data(com0_rd),
-		.interrupt(com0_interrupt),
-		.leds(LED),
-		.switches(SWITCH),
-		.uart0_rx(RX),
-		.uart0_tx(TX),
-		.key1(~KEY[1])
-	);
-
 endmodule