Implemented jump instr

UCL_project_y3.qsf

@@ -69,15 +69,13 @@ set_location_assignment PIN_B9 -to switches[2]
 set_location_assignment PIN_M15 -to switches[3]
 set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
 set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation
-set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH risc_test -section_id eda_simulation
+set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH testbench_1 -section_id eda_simulation
 set_global_assignment -name EDA_TEST_BENCH_NAME testbench_1 -section_id eda_simulation
 set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id testbench_1
 set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME testbench_1 -section_id testbench_1
 set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
 set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
 set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
-set_global_assignment -name SYSTEMVERILOG_FILE src/risc/alu.sv
-set_global_assignment -name SYSTEMVERILOG_FILE src/risc/risc.sv
 set_global_assignment -name MIF_FILE memory/rom_test.mem
 set_global_assignment -name SYSTEMVERILOG_FILE src/datapath.sv
 set_global_assignment -name SYSTEMVERILOG_FILE src/blocks/instr_mem.sv
@@ -88,14 +86,10 @@ set_global_assignment -name SYSTEMVERILOG_FILE src/blocks/alu.sv
 set_global_assignment -name SYSTEMVERILOG_FILE src/io_unit.sv
 set_global_assignment -name SYSTEMVERILOG_FILE src/general.sv
 set_global_assignment -name SYSTEMVERILOG_FILE src/controller.sv
-set_global_assignment -name EDA_TEST_BENCH_NAME risc_test -section_id eda_simulation
-set_global_assignment -name EDA_DESIGN_INSTANCE_NAME NA -section_id risc_test
-set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME risc_test -section_id risc_test
-set_global_assignment -name EDA_TEST_BENCH_FILE src/risc/alu.sv -section_id risc_test
 set_global_assignment -name EDA_TEST_BENCH_FILE src/blocks/reg_file_tb.sv -section_id testbench_1
 set_global_assignment -name EDA_TEST_BENCH_FILE src/blocks/memory.sv -section_id testbench_1
 set_global_assignment -name EDA_TEST_BENCH_FILE src/blocks/alu.sv -section_id testbench_1
-set_global_assignment -name EDA_TEST_BENCH_FILE src/controller.sv -section_id testbench_1
 set_global_assignment -name EDA_TEST_BENCH_FILE src/datapath.sv -section_id testbench_1
 set_global_assignment -name EDA_TEST_BENCH_FILE src/cpu.sv -section_id testbench_1
+set_global_assignment -name EDA_TEST_BENCH_FILE src/controller.sv -section_id testbench_1
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

memory/test.asm

@@ -0,0 +1,9 @@
+// Initialise
+Start:
+CPY $rb 0x01
+CPY $rc 0x03
+While:
+ADD $ra $rb
+JEQ $ra $rc Start
+JMP While
+

src/blocks/alu.sv

@@ -8,15 +8,28 @@ module alu(op, srcA, srcB, result, zero);
 	output word			result;
 	output logic		zero;
 	
+	logic [2:0]xop;
+	logic [2:0]shamt;
+	
 	always_comb begin
+	xop = srcB[7:5];
+	shamt = srcB[2:0];
 	case(op)
+		ALU_CPY: result = srcB;
 		ALU_ADD: result = srcA + srcB;
 		ALU_SUB: result = srcA - srcB;
 		ALU_AND: result = srcA & srcB;
 		ALU_OR : result = srcA | srcB;
-		ALU_SLT: result = srcA > srcB;
-		ALU_NOT: result = ~srcB;
-		ALU_NOP: result = srcA;
+		ALU_XOR: result = srcA ^ srcB;
+		ALU_GT : result = srcA > srcB;
+		ALU_EXT: begin
+				case(xop)
+						3'b000: result = srcA << shamt;
+						3'b001: result = srcA >> shamt;
+						3'b010: result = srcA >>> shamt;
+						default: result = srcA;
+				endcase
+		end
 		default: result = 0;
 	endcase
 	end
@@ -32,32 +45,64 @@ module alu_tb;
 	alu ALU(op, srcA, srcB, result, zero);
 	
 	initial begin
-		op = ALU_NOP;
+		op = ALU_CPY;
 		srcA = 120;
 		srcB = 100;
 		#5ns;
 		assert(result == srcA);
+		
 		op = ALU_ADD;
 		#5ns;
 		assert(result == 220);
+		
 		op = ALU_SUB;
 		#5ns;
 		assert(result == 20);
+		
 		op = ALU_AND;
 		// 01100100 & 01111000 = 01100000
 		#5ns;
 		assert(result == 96);
+
 		op = ALU_OR;
 		// 01100100 | 01111000 = 01111100
 		#5ns;
 		assert(result == 124);
-		op = ALU_SLT;
+		
+		op = ALU_XOR;
+		#5ns;
+		assert(result == 28);
+		
+		op = ALU_GT;
 		#5ns;
 		assert(result == 1);
+		
 		srcB = 140;
 		#5ns;
 		assert(result == 0);
 		assert(zero == 1);
+		
+		op = ALU_EXT;
+		srcB = 8'b000xx000;
+		#5ns;
+		assert(result == srcA);
+		
+		srcB = 8'b000xx001;
+		#5ns;
+		assert(result == 240);
+		
+		srcB = 8'b001xx001;
+		#5ns;
+		assert(result == 60);
+		
+		srcB = 8'b001xx010;
+		#5ns;
+		assert(result == 30);
+		
+		srcB = 8'b010xx100;
+		#5ns;
+		// 01111000 >>> 4 = 10000111
+		assert(result == 71);
 		$stop;
 	end
 

src/blocks/memory.sv

@@ -2,8 +2,8 @@ import project_pkg::*;
 
 module memory(
 		input 	logic 	clk, we,
-		input 	word 	a, rd, 
-		output 	word 	wd
+		input 	word 	a, wd, 
+		output 	word 	rd
 	);	
 	
 	logic [word_size-1:0]memory[mem_size-1:0];
@@ -17,7 +17,9 @@ endmodule
 module memory_tb;
 	logic clk, wr_en;
 	word addr, wr_data, rd_data;
-	
+	memory MEM(clk, wr_en, addr, wr_data, rd_data);
+	localparam csize = 10;
+
 	initial begin
 		clk = 0;
 		forever #5ns clk = ~clk;
@@ -26,14 +28,14 @@ module memory_tb;
 	initial begin
 		addr = 0;
 		wr_en = 1;
-		for(int i=0;i<mem_size;i++) begin
+		for(int i=0;i<csize;i++) begin
 			wr_data = i;
 			addr = i;
 			#10ns;
 		end
 		wr_en = 0;
 		wr_data = 0;
-		for(int i=0;i<mem_size;i++) begin
+		for(int i=0;i<csize;i++) begin
 			#10ns;
 			addr = i;
 			assert(rd_data == i);

src/controller.sv

@@ -1,86 +1,28 @@
 import project_pkg::*;
 
-module controller(instr, zero, alu_op, mem_wr, reg_wr, pc_src, alu_src, mem_to_reg, instr_op, rs, rt);
+module controller(instr, zero, alu_op, mem_wr, reg_wr, pc_src, rimm, alu_src, mem_to_reg, instr_op, rd, rs);
 	input word instr;
 	input logic zero; // That's from ALU for J instructions
 	output e_alu_op alu_op;
-	output logic mem_wr, reg_wr, alu_src, mem_to_reg, pc_src;
+	output logic mem_wr, reg_wr, rimm, mem_to_reg, pc_src, alu_src;
 	output e_instr instr_op;
-	output e_reg rs, rt;
+	output e_reg rs, rd;
 	// Instruction decoding
 	assign instr_op 	= e_instr'(instr[7:4]);
-	assign rs 			= e_reg'(instr[3:2]);
-	assign rt 			= e_reg'(instr[1:0]);
-
-	always_comb begin
-	case(instr_op)
-			NOP : begin
-					alu_op = ALU_NOP;
-					reg_wr = 0;
-			end
-			ADD : begin
-					alu_op = ALU_ADD;
-					reg_wr = 1;
-			end
-			ADDI: begin
-					alu_op = ALU_ADD;
-					reg_wr = 1;
-			end
-			SUB : begin
-					alu_op = ALU_SUB;
-					reg_wr = 1;
-			end
-			AND : begin
-					alu_op = ALU_AND;
-					reg_wr = 1;
-			end
-			OR  : begin
-					alu_op = ALU_OR;
-					reg_wr = 1;
-			end
-			NOT : begin
-					alu_op = ALU_NOT;
-					reg_wr = 1;
-			end
-			LW  : begin
-					alu_op = ALU_NOP;
-					reg_wr = 0;
-			end
-			SW  : begin
-					alu_op = ALU_NOP;
-					reg_wr = 0;
-			end
-			WO  : begin
-					alu_op = ALU_NOP;
-					reg_wr = 0;
-			end
-			RO  : begin
-					alu_op = ALU_NOP;
-					reg_wr = 1;
-			end
-			COPY: begin
-					alu_op = ALU_NOP;
-					reg_wr = 1;
-			end
-			JEQ : begin
-					alu_op = ALU_SUB;
-					reg_wr = 0;
-			end
-			ZERO: begin
-					alu_op = ALU_NOP;
-					reg_wr = 0;
-			end
-			default: begin
-					alu_op = ALU_NOP;
-					reg_wr = 0;
-			end
-	endcase
-	end
+	assign rd 			= e_reg'(instr[3:2]);
+	assign rs 			= e_reg'(instr[1:0]);
+	
+	e_alu_op alu_subsel;
+	assign alu_subsel = (instr_op == JEQ) ? ALU_SUB : ALU_CPY;
+	assign alu_op = instr_op[3] ? alu_subsel : e_alu_op'(instr_op[2:0]);
+	assign reg_wr = ~instr_op[3] | instr_op == LW; 
 	
 	assign mem_wr = instr_op == SW;
 	assign mem_to_reg = instr_op == LW;
-	assign pc_src = zero && instr_op == JEQ;
-	assign alu_src = instr_op == ADDI;	
+	assign pc_src = (zero && instr_op == JEQ) | instr_op == JMP;
+	
+	assign alu_src = (instr_op == CPY & rd == rs);	
+	assign rimm = (alu_src) | instr_op == JEQ;	
 
 endmodule
 
@@ -95,7 +37,7 @@ module controller_tb;
 		instr = 8'h00;
 		zero = 1;
 		#5ns;
-		assert(alu_op == ALU_NOP);
+		//assert(alu_op == ALU_NOP);
 		assert(mem_wr == 0);
 		assert(reg_wr == 0);
 		assert(pc_src == 0);
@@ -143,7 +85,7 @@ module controller_tb;
 		assert(mem_to_reg == 0);
 		instr = 8'h60;
 		#5ns;
-		assert(alu_op == ALU_NOT);
+		//assert(alu_op == ALU_NOT);
 		assert(mem_wr == 0);
 		assert(reg_wr == 1);
 		assert(pc_src == 0);
@@ -151,7 +93,7 @@ module controller_tb;
 		assert(mem_to_reg == 0);
 		instr = 8'h70;
 		#5ns;
-		assert(alu_op == ALU_NOP);
+		//assert(alu_op == ALU_NOP);
 		assert(mem_wr == 0);
 		assert(reg_wr == 1);
 		assert(pc_src == 0);
@@ -159,7 +101,7 @@ module controller_tb;
 		assert(mem_to_reg == 1);
 		instr = 8'h80;
 		#5ns;
-		assert(alu_op == ALU_NOP);
+		//assert(alu_op == ALU_NOP);
 		assert(mem_wr == 1);
 		assert(reg_wr == 0);
 		assert(pc_src == 0);
@@ -167,7 +109,7 @@ module controller_tb;
 		assert(mem_to_reg == 0);
 		instr = 8'hB0;
 		#5ns;
-		assert(alu_op == ALU_NOP);
+		//assert(alu_op == ALU_NOP);
 		assert(mem_wr == 0);
 		assert(reg_wr == 1);
 		assert(pc_src == 0);

src/cpu.sv

@@ -7,15 +7,15 @@ module cpu(clk, rst, instr, imm, pc, mem_addr, mem_wr_en, mem_wr_data, mem_rd_da
 	output word pc, mem_addr, mem_wr_data;
 
 	// Controller
-	logic alu_zero, pc_src, reg_wr, alu_src, mem_to_reg;
+	logic alu_zero, pc_src, reg_wr, rimm, alu_src, mem_to_reg;
 	e_instr instr_op;
-	e_reg rs, rt;
+	e_reg rd, rs;
 	e_alu_op alu_op;
 	
-	controller CTRL(instr, alu_zero, alu_op, mem_wr_en, reg_wr, pc_src, alu_src, mem_to_reg, instr_op, rs, rt);
+	controller CTRL(instr, alu_zero, alu_op, mem_wr_en, reg_wr, pc_src, rimm, alu_src, mem_to_reg, instr_op, rd, rs);
 
 	// Datapath
-	datapath DPATH(clk, rst, rs, rt, imm, alu_op, reg_wr, pc_src, alu_src, mem_to_reg, pc, mem_addr, mem_rd_data, alu_zero, mem_wr_data);	
+	datapath DPATH(clk, rst, rd, rs, imm, alu_op, reg_wr, pc_src, rimm, alu_src, mem_to_reg, pc, mem_addr, mem_rd_data, alu_zero, mem_wr_data);	
 endmodule
 
 module cpu_tb;
@@ -23,9 +23,12 @@ module cpu_tb;
 	word pc, instr, imm, mem_addr, mem_data, mem_rd_data;	
 	cpu CPU(clk, rst, instr, imm, pc, mem_addr, mem_wr, mem_data, mem_rd_data);
 	// Instruction memory
-	instr_mem #("/home/min/devel/fpga/ucl_project_y3/memory/rom_test.mem") IMEM(pc, instr, imm);
+	instr_mem #("/home/min/devel/fpga/ucl_project_y3/memory/test.mem") IMEM(pc, instr, imm);
 	// System memory
-	memory RAM(clk, mem_addr, mem_data, mem_rd_data, mem_wr);	
+	memory RAM(clk, mem_wr, mem_addr, mem_data, mem_rd_data);	 word outvalue;
+	always_ff@(negedge mem_wr)
+			if(mem_addr == 8'hFF) outvalue <= mem_data;
+
 	initial begin
 		clk = 0;
 		forever #5ns clk = ~clk;
@@ -35,7 +38,5 @@ module cpu_tb;
 		rst = 1;
 		#10ns;
 		rst = 0;
-		#100ns;
-		$stop;
 	end
 endmodule

src/datapath.sv

@@ -1,8 +1,8 @@
 import project_pkg::*;
 
-module datapath(clk, rst, rs, rt, imm, alu_op, reg_wr, pc_src, alu_src, mem_to_reg, pc, alu_out, mem_data, alu_zero, mem_wr_data);
-	input logic clk, rst, reg_wr, pc_src, alu_src, mem_to_reg;
-	input e_reg rs, rt;
+module datapath(clk, rst, rd, rs, imm, alu_op, reg_wr, pc_src, rimm, alu_src, mem_to_reg, pc, alu_out, mem_data, alu_zero, mem_wr_data);
+	input logic clk, rst, reg_wr, pc_src, rimm, mem_to_reg, alu_src;
+	input e_reg rd, rs;
 	input e_alu_op alu_op;
 	input word imm, mem_data;
 	output word pc, alu_out, mem_wr_data;
@@ -11,25 +11,27 @@ module datapath(clk, rst, rs, rt, imm, alu_op, reg_wr, pc_src, alu_src, mem_to_r
 	// Reg File
 	word reg_rd_d1, reg_rd_d2, reg_wr_d;
 	e_reg reg_rd_a1, reg_rd_a2, reg_wr_a;
-	assign reg_rd_a1 = rs;
-	assign reg_rd_a2 = rt;
-	assign reg_wr_a = rs;
+	assign reg_rd_a1 = rd;
+	assign reg_rd_a2 = rs;
+	assign reg_wr_a = rd;
 	assign reg_wr_d = (mem_to_reg) ? mem_data : alu_out;
 	reg_file RFILE(clk, rst, reg_rd_a1, reg_rd_a2, reg_rd_d1, reg_rd_d2, reg_wr_a, reg_wr_d, reg_wr);
 
 	// Mem output data
-	assign mem_wr_data = reg_rd_a2;
+	assign mem_wr_data = reg_rd_d1;
 
 	// ALU
 	word alu_srcA, alu_srcB;
 	assign alu_srcA = reg_rd_d1;
-	assign alu_srcB = (alu_src) ? imm : reg_rd_d2;
+	assign alu_srcB = alu_src ? imm : reg_rd_d2;
 	alu ALU(alu_op, alu_srcA, alu_srcB, alu_out, alu_zero);
 	
 	// Program counter
 	word pcn; 	// PC next
 	word pcj;   // PC jump, +2 if imm used otherwise +1
-	assign pcj = (alu_src) ? pc + 2 : pc + 1;
+	logic [0:1]pcadd;
+	assign pcadd = (rimm) ? 2 : 1;
+	assign pcj =  pc + pcadd;
 	//assign pcj = pc + 1;
 	assign pcn = (pc_src) ? imm : pcj;
 	always_ff@(posedge clk) begin
@@ -39,11 +41,11 @@ module datapath(clk, rst, rs, rt, imm, alu_op, reg_wr, pc_src, alu_src, mem_to_r
 endmodule
 
 module datapath_tb;
-	logic clk, rst, reg_wr, pc_src, alu_src, mem_to_reg, alu_zero;
+	logic clk, rst, reg_wr, pc_src, rimm, mem_to_reg, alu_zero;
 	e_reg rs, rt;
 	e_alu_op alu_op;
 	word imm, mem_data, pc, alu_out;
-	datapath DPATH(clk, rst, rs, rt, imm, alu_op, reg_wr, pc_src, alu_src, mem_to_reg, pc, alu_out, mem_data, alu_zero);
+	datapath DPATH(clk, rst, rs, rt, imm, alu_op, reg_wr, pc_src, rimm, mem_to_reg, pc, alu_out, mem_data, alu_zero);
 
 	initial begin
 		clk = 0;
@@ -54,11 +56,11 @@ module datapath_tb;
 		rst = 1;
 		reg_wr = 0;
 		pc_src = 0;
-		alu_src = 0;
+		rimm = 0;
 		mem_to_reg = 0;
-		rs = RegA;
-		rt = RegA;
-		alu_op = ALU_NOP;
+		rs = ra;
+		rt = ra;
+		alu_op = ALU_CPY;
 		imm = 8'h00;
 		mem_data = 8'h00;
 		#10ns;
@@ -67,16 +69,16 @@ module datapath_tb;
 		mem_to_reg = 1;
 		mem_data = 8'h7A;
 		#10ns;
-		rs = RegB;
+		rs = rb;
 		mem_data = 8'h8A;
 		#10ns;
-		rs = RegC;
+		rs = rc;
 		mem_data = 8'h9A;
 		#10ns;
-		rs = RegD;
+		rs = re;
 		mem_data = 8'hFD;
 		#10ns;
-		rs = RegA;
+		rs = ra;
 		#10ns;
 		$stop;
 	end

src/general.sv

@@ -1,7 +1,7 @@
 package project_pkg;
 		
 	localparam word_size = 8;
-	localparam mem_size = 8;
+	localparam mem_size = 256;
 	localparam rom_size = 256;
 	localparam reg_size = 4;
 
@@ -10,40 +10,43 @@ package project_pkg;
 	typedef logic [reg_addr_size-1:0] regAddr;
 	
 	typedef enum logic [1:0] {
-		RegA = 2'b00,
-		RegB = 2'b01,
-		RegC = 2'b10,
-		RegD = 2'b11
+		ra = 2'b00,
+		rb = 2'b01,
+		rc = 2'b10,
+		re = 2'b11
 	} e_reg;
 	
 	typedef enum logic [3:0] { 
-		NOP =4'h0,	// No operation
-		ADD =4'h1,  // $rs = $rs + $rt
-		ADDI=4'h2,  // $rs = $rs + $imm
-		SUB =4'h3,  // $rs = $rs - $rt
-		AND =4'h4,  // $rs = $rs & $rt
-		OR  =4'h5,  // $rs = $rs | $rt
-		NOT =4'h6,  // $rs = ~$rt
-		LW  =4'h7,  // Load word from $rt to $rs
-		SW  =4'h8,  // Save word from $rt to $rs
-		WO  =4'h9,  // Write $rs to output
-		RO  =4'hA,  // Read output to $rs
-		COPY=4'hB,  // $rs = $rt
-		JEQ =4'hC,  // Jump to $imm if $rs == $rt
-		ZERO=4'hD,  // $rs = 0x00
-		__0 =4'hE,  //
-		__1 =4'hF   //		
+		// [ xxxx xx xx ] => [ inst rd rs ]
+		// mp: Memory page
+		// cp: Co-processor, 0x00 = RAM, 0x01 = ROM, 0x02 = FPU, 0x03 = GPIO
+		CPY =4'b0000,  // $rd = imm if rd == rs else $rd = $rs
+		ADD =4'b0001,  // $rd = $rd + $rs
+		SUB =4'b0010,  // $rd = $rd - $rs
+		AND =4'b0011,  // $rd = $rd & $rs
+		OR  =4'b0100,  // $rd = $rd | $rs
+		XOR =4'b0101,  // $rd = $rd ^ $rs
+		GT  =4'b0110,  // $rd = $rd > $rs
+		EXT =4'b0111,  // $rd binary [ xxxxx xxx ], first 5 bits means shift operation, last 3 means shift amount
+		LW  =4'b1000,  // $rd = mem[$mp + $rs]
+		SW  =4'b1001,  // mem[$mp + $rs] = $rd
+		JEQ =4'b1010,  // Jump to imm if $rd == $rs
+		JMP =4'b1011,  // Jump to case rs 00: $rd  01: imm 10: $rd+imm 11: ??
+		SET =4'b1100,  // Set memory page $mp = $rd
+		SCO =4'b1101,  // Set co-processor $cp = $rs
+		PUSH=4'b1110,  // Push $rd to top of stack
+		POP =4'b1111   // Pop stack to $rd
 	} e_instr;
-	
-	typedef enum logic [2:0] { 
-		ALU_ADD=3'b000,
-		ALU_SUB=3'b001,
-		ALU_AND=3'b010,
-		ALU_OR =3'b011,
-		ALU_SLT=3'b100,
-		ALU_NOT=3'b101,
-		ALU___0=3'b110,
-		ALU_NOP=3'b111
+
+	typedef enum logic [2:0] {
+		ALU_CPY = 3'b000,
+		ALU_ADD = 3'b001,
+		ALU_SUB = 3'b010,
+		ALU_AND = 3'b011,
+		ALU_OR  = 3'b100,
+		ALU_XOR = 3'b101,
+		ALU_GT  = 3'b110,
+		ALU_EXT = 3'b111
 	} e_alu_op;
 	
 	

src/io_unit.sv

@@ -1,3 +1,4 @@
+import project_pkg::word;
 
 module io_unit(switches, keys, leds);
 	input  logic [3:0]switches;
@@ -9,7 +10,9 @@ module io_unit(switches, keys, leds);
 	logic mem_wr;
 	word pc, instr, imm, mem_addr, mem_data, mem_rd_data;	
 	cpu CPU(clk, rst, instr, imm, pc, mem_addr, mem_wr, mem_data, mem_rd_data);
-	instr_mem #("/home/min/devel/fpga/ucl_project_y3/memory/rom_test.mem") IMEM(pc, instr, imm);	
-	memory RAM(clk, mem_addr, mem_data, mem_rd_data, mem_wr);	
+	// Instruction memory
+	instr_mem #("/home/min/devel/fpga/ucl_project_y3/memory/test.mem") IMEM(pc, instr, imm);
+	// System memory
+	memory RAM(clk, mem_wr, mem_addr, mem_data, mem_rd_data);	
 
 endmodule