Final report WIP

docs/final_report/4-theory.tex

@@ -6,3 +6,10 @@ Have you made any deductions from it that you are now testing?
 What mathematical bases must be understood in order to interpret your results in Chapter 5?
 Give the reader a solid understanding of the foundations here.
 \fi
+
+
+\textbf{Decided design criteria:}
+\begin{description}
+	\item[$\bullet$] Minimal instruction size
+	\item[$\bullet$] Minimalistic design
+\end{description}

docs/final_report/5-methods.tex

@@ -7,4 +7,124 @@ How did you set up the simulation: what mesh values, for example, did you use?
 
 Provide enough detail that your work can be duplicated by someone else.
 Be precise and use the correct units.
-\fi
+\fi
+
+
+
+
+
+This section describes methods and design choices used to construct two processors.
+
+\subsection{Machine Code}\label{subsec:machine_code}
+
+\subsubsection{RISC}
+As the aim of instruction size to be as minimal as possible, RISC instruction decided to be 8bits with optional additional immediate value from 1 to 3 bytes. Immediate values are explained in section \ref{subsec:imm_values}.
+
+Decision was made to have instruction compose of operation code two operands - source/destination and source, which is similar to x86 architecture rather than MIPS. Three possible combinations of register address sizes are possible in such case from one to three bits. Two was selected as it allow having four general purpose registers which is sufficient for most applications, and allow four bits for operation code - allowing up to 16 instructions. 
+
+Due to small amount of available operation codes and not all instructions requiring two operands (for example \texttt{JUMP} instruction may not need any operands or could use one operand to have address offset), other two type instructions are added to the design - with one and zero operands. See figure \ref{fig:risc_machinecode}. This enabled processor to have 45 different instructions while maintaining minimal instruction size. Final design has:
+\begin{description}[labelindent=1cm, labelsep=1em]
+	\item[$\bullet$ \textbf{8 }]  2-operand instructions
+	\item[$\bullet$ \textbf{32}]  1-operand instructions
+	\item[$\bullet$ \textbf{5 }]  0-operand instructions
+\end{description}
+Full list of RISC instructions are listed in table \ref{tab:risc_instructions} in \nameref{sec:appendix} section.
+
+
+\definecolor{c1}{HTML}{ff7568} 
+\definecolor{c2}{HTML}{8cbfff} 
+\definecolor{c3}{HTML}{a6ddb7} 
+
+
+\begin{gather*}
+\scalebox{0.8}{2 operands:}~
+\underbrace{
+	\colorbox{c1}{0}\,
+	\colorbox{c1}{1}\,
+	\colorbox{c1}{2}\,
+	\colorbox{c1}{3}
+}_\text{op. code}
+\underbrace{
+	\colorbox{c2}{4}\,
+	\colorbox{c2}{5}
+}_\text{dst.}
+\underbrace{
+	\colorbox{c3}{6}\,
+	\colorbox{c3}{7}
+}_\text{src.}
+\\
+\scalebox{0.8}{1 operand:}~
+\underbrace{
+	\colorbox{c1}{0}\,
+	\colorbox{c1}{1}\,
+	\colorbox{c1}{2}\,
+	\colorbox{c1}{3}
+}_\text{op. code}
+\underbrace{
+	\colorbox{c2}{4}\,
+	\colorbox{c2}{5}
+}_\text{dst.}
+\underbrace{
+	\colorbox{c1}{6}\,
+	\colorbox{c1}{7}
+}_\text{op. c.}\\
+\scalebox{0.8}{0 operands:}~
+\underbrace{
+	\colorbox{c1}{0}\,
+	\colorbox{c1}{1}\,
+	\colorbox{c1}{2}\,
+	\colorbox{c1}{3}\,
+	\colorbox{c1}{4}\,
+	\colorbox{c1}{5}\,
+	\colorbox{c1}{6}\,
+	\colorbox{c1}{7}
+}_\text{operation code}
+\end{gather*}
+\begin{center}
+\captionof{figure}{\textit{RISC instructions composition. Number inside box represents bit index. Destination (dst.) bits represents of source and destination register address.}}
+\label{fig:risc_machinecode}
+\end{center}
+
+\subsubsection{OISC}
+
+As OISC requires only a single instruction, composition of instruction mainly requires two parts - source and destination. To allow higher instruction flexibility a immediate bit has been added to replace source address by immediate value. Composition of finalised machine code is shown in figure \ref{fig:oisc_machinecode}. 
+
+\begin{gather*}
+\underbrace{
+	\colorbox{c1}{0}
+}_\text{imm.}
+\underbrace{
+	\colorbox{c2}{1}\,
+	\colorbox{c2}{2}\,
+	\colorbox{c2}{3}\,
+	\colorbox{c2}{4}\,
+}_\text{destination}
+\underbrace{
+	\colorbox{c3}{5}\,
+	\colorbox{c3}{6}\,
+	\colorbox{c3}{7}\,
+	\colorbox{c3}{8}\,
+	\colorbox{c3}{9}\,
+	\colorbox{c3}{10}\,
+	\colorbox{c3}{11}\,
+	\colorbox{c3}{12}
+}_\text{source}
+\end{gather*}
+
+\begin{center}
+\captionof{figure}{\textit{OISC instruction composition. Number inside box represents bit index.}}
+\label{fig:oisc_machinecode}
+\end{center}
+
+Decision was made to have source address to be eight bits to allow it be replaced with immediate value. Destination address was chosen to be as minimal as possible, leaving only four bits or 16 possible destinations. Final design has \textbf{15} destination and \textbf{41} source addresses. This is not the most space efficient design as 41 source addresses would require only six bits for address, wasting two bits every time non-immediate source is used.
+
+Full list of OISC sources and destinations are listed in table \ref{tab:oisc_instructions} in \nameref{sec:appendix} section.
+
+\subsection{Immediate values}\label{subsec:imm_values}
+
+
+\subsection{Arithmetic Logic Unit}\label{subsec:alu}
+
+\subsection{Memory}\label{subsec:memory}
+
+

docs/final_report/8-appendix.tex

@@ -1 +1,185 @@
-This is appendix
+
+
+
+\arrayrulecolor{black}
+\begin{longtable}[h!]{| l | p{.70\textwidth} | c |}
+\caption{Instruction set for RISC processor. * Required immediate size in bytes}
+\label{table:risc_instructions}\\
+
+\hline 
+\rowcolor[rgb]{0.82,0.82,0.82}
+Instr. & Description & I-size *\\\hline
+\endhead		
+
+\arrayrulecolor{black}\hline
+\endfoot
+
+\multicolumn{3}{|c|}{
+	\cellcolor[rgb]{0.7,0.7,1}\textit{2 register instructions}} \\\hline
+\arrayrulecolor[rgb]{0.82,0.82,0.82}
+
+MOVE & Copy value from one register to other & 0 \\\hline
+ADD  & Arithmetical addition & 0 \\
+SUB  & Arithmetical subtraction & 0  \\
+AND  & Logical AND & 0 \\
+OR   & Logical OR & 0 \\
+XOR  & Logical XOR & 0 \\
+MUL  & Arithmetical multiplication & 0 \\
+DIV  & Arithmetical division (inc. modulus) & 0 \\
+
+
+\arrayrulecolor{black}\hline
+\multicolumn{3}{|c|}{
+	\cellcolor[rgb]{0.7,0.7,1}\textit{1 register instructions}} \\
+\hline\arrayrulecolor[rgb]{0.82,0.82,0.82}
+
+
+COPY0 & Copy intimidate to a register 0 & 1 \\
+COPY1 & Copy intimidate to a register 1 & 1 \\
+COPY2 & Copy intimidate to a register 2 & 1 \\
+COPY3 & Copy intimidate to a register 3 & 1 \\\hline
+
+ADDC & Arithmetical addition with carry bit& 0 \\
+ADDI & Arithmetical addition with immediate & 1 \\
+SUBC & Arithmetical subtraction with carry bit & 0 \\
+SUBI & Arithmetical subtraction with immediate & 1 \\\hline
+
+ANDI & Logical AND with immediate & 1 \\
+ORI  &  Logical OR with immediate & 1 \\
+XORI &  Logical XOR with immediate & 1 \\\hline
+
+CI0  & Replace intimidate value byte 0 for next instruction & 1 \\
+CI1  & Replace intimidate value byte 1 for next instruction & 1 \\
+CI2  & Replace intimidate value byte 2 for next instruction & 1 \\\hline
+
+SLL  & Shift left logical & 1 \\
+SRL  & Shift right logical & 1 \\
+SRA  & Shift right arithmetical & 1 \\\hline
+
+LWHI & Load word (high byte) & 3 \\
+SWHI & Store word (high byte, reg. only) & 0 \\
+LWLO & Load word (low byte) & 3 \\
+SWLO & Store word (low byte, stores high byte reg.) & 3 \\\hline
+
+INC  & Increase by 1 & 0 \\
+DEC  & Decrease by 1 & 0 \\
+GETAH& Get ALU high byte reg. (only for MUL \& DIV \& ROL \& ROR) & 0 \\
+GETIF& Get interrupt flags & 0 \\\hline
+
+PUSH & Push to stack & 0 \\
+POP  & Pop from stack & 0 \\
+COM  & Send/Receive to/from com. block & 1 \\\hline
+
+BEQ  & Branch on equal & 3 \\
+BGT  & Branch on greater than & 3 \\
+BGE  & Branch on greater equal than & 3 \\
+BZ   & Branch on zero & 2 \\
+
+\arrayrulecolor{black}\hline
+\multicolumn{3}{|c|}{
+	\cellcolor[rgb]{0.7,0.7,1}\textit{0 register instructions}
+} \\
+\hline\arrayrulecolor[rgb]{0.82,0.82,0.82} 
+
+CALL & Call function, put return to stack & 2 \\
+RET  & Return from function & 0 \\
+JUMP & Jump to address & 2 \\
+RETI & Return from interrupt & 0 \\
+INTRE& Set interrupt entry pointer & 2 \\\hline
+
+
+\end{longtable}	
+
+\arrayrulecolor{black}
+\begin{longtable}[h!]{| l | p{0.8\textwidth} |}
+	\caption{Instructions for OISC processor.}
+	\label{table:oisc_instructions}\\
+	
+	\hline 
+	\rowcolor[rgb]{0.82,0.82,0.82}
+	Name & Description \\\hline
+	\endhead		
+	
+	\arrayrulecolor{black}\hline
+	\endfoot
+	
+	\multicolumn{2}{|c|}{
+		\cellcolor[rgb]{0.7,0.7,1}\textit{Destination Addresses}} \\\hline
+	\arrayrulecolor[rgb]{0.82,0.82,0.82}
+	
+	ACC0 & Set ALU source A accumulator \\
+	ACC1 & Set ALU source B accumulator \\\hline
+	BR0  & Set Branch pointer register (low byte) \\
+	BR1  & Set Branch pointer register (high byte) \\
+	BRZ  & If source value is 0, set program counter to branch pointer \\\hline
+	STACK& Push value to stack \\
+	MEM0 & Set Memory pointer register (low byte) \\
+	MEM1 & Set Memory pointer register (middle byte) \\
+	MEM2 & Set Memory pointer register (high byte) \\
+	MEMHI& Save high byte to memory at memory pointer \\
+	MEMLO& Save low byte to memory at memory pointer \\\hline
+	COMA & Set communication block address register \\
+	COMD & Send value to communication block \\\hline
+	REG0 & Set general purpose register 0 \\
+	REG1 & set general purpose register 1 \\
+	
+	\arrayrulecolor{black}\hline
+	\multicolumn{2}{|c|}{
+		\cellcolor[rgb]{0.7,0.7,1}\textit{Source Addresses}} \\
+	\hline\arrayrulecolor[rgb]{0.82,0.82,0.82}
+	
+	NULL & Get constant 0 \\
+	ALU0 & Get value at ALU source A accumulator \\
+	ALU1 & Get value at ALU source B accumulator \\\hline
+	
+	ADD  & Get Arithmetical addition of ALU sources \\
+	ADDC & Get Arithmetical addition carry \\
+	ADC  & Get Arithmetical addition of ALU sources and carry \\\hline
+	
+	SUB  & Get Arithmetical subtraction of ALU sources \\
+	SUBC & Get Arithmetical subtraction carry \\
+	SBC  & Get Arithmetical subtraction of ALU sources and carry \\\hline
+	
+	AND  & Get Logical AND of ALU sources \\
+	OR   & Get Logical OR of ALU sources \\
+	XOR  & Get Logical XOR of ALU sources \\\hline
+	
+	SLL  & Get ALU source A shifted left by source B \\
+	SRL  & Get ALU source A shifted right by source B \\
+	ROL  & Get rolled off value from previous SLL instance \\
+	ROR  & Get rolled off value from previous SRL instance \\\hline
+	
+	MULLO& Get Arithmetical multiplication of ALU sources (low byte) \\
+	MULHI& Get Arithmetical multiplication of ALU sources (high byte) \\
+	DIV  & Get Arithmetical division of ALU sources \\
+	MOD  & Get Arithmetical modulus of ALU sources \\\hline
+	
+	EQ   & Check if ALU source A is equal to source B \\
+	GT   & Check if ALU source A is greater than source B \\
+	GE   & Check if ALU source A is greater or equal to source B \\
+	NE   & Check if ALU source A is not equal to source B \\
+	LT   & Check if ALU source A is less than source B \\
+	LE   & Check if ALU source A is less or equal to to source B \\\hline
+	
+	BR0  & Get Branch pointer register value (low byte) \\
+	BR1  & Get Branch pointer register value (high byte) \\	
+	PC0  & Get Program counter value (low byte) \\
+	PC1  & Get Program counter value (high byte) \\\hline
+	
+	MEM0 & Get Memory pointer register value (low byte) \\
+	MEM1 & Get Memory pointer register value (middle byte) \\
+	MEM2 & Get Memory pointer register value (high byte) \\
+	MEMHI& Load high byte from memory at memory pointer \\
+	MEMLO& Load low byte from memory at memory pointer \\\hline
+	
+	STACK& Pop value from stack \\
+	ST0  & Get stack address value (low byte) \\
+	ST1  & Get stack address value (high byte) \\
+	
+	COMA & Get communication block address register value \\
+	COMD & Read value from communication block \\\hline
+	
+	REG0 & Get value from general purpose register 0 \\
+	REG1 & Get value from general purpose register 1 \\
+	
+\end{longtable}	

docs/final_report/index.tex

@@ -10,6 +10,10 @@
 \usepackage{graphicx}
 \usepackage{pdflscape}
 \usepackage{svg}
+\usepackage{caption}
+\usepackage{enumitem}
+\usepackage{lipsum}
+
 
 
 \usepackage{tabularx}
@@ -41,7 +45,7 @@
 		\newcommand{\HRule}{\rule{\linewidth}{0.5mm}}
 		\begin{tikzpicture}[remember picture, overlay]
 		\node [anchor=north east, inner sep=0pt]  at (current page.north east)
-		{\includegraphics[width=21cm]{../resources/ucl-banner-dl-port-outline.eps}};
+		{\includegraphics[width=21cm]{../resources/graphics/ucl-banner-dl-port-outline.eps}};
 		\end{tikzpicture}\\[3cm]
 		\center
 		
@@ -99,10 +103,11 @@
 	\input{6-results.tex}
 	\section{Conclusion}\label{sec:conclusion}
 	\input{7-conclusion.tex}
-	\section{Appendix}\label{sec:appendix}
-	\input{8-appendix.tex}
 	\section{References}
 	\printbibliography
 	\end{multicols}
+	\pagebreak
+	\section{Appendix}\label{sec:appendix}
+	\input{8-appendix.tex}
 	
 \end{document}