Interrupts WIP

This is initial work to implement interrupts to RISC8. Added instruction
INSTRE to set interrupt entry location.

Makefile

@@ -37,7 +37,7 @@ define execute-gentable
 $(GENTABLE_BIN) $(1) $(1:.csv=.sv)
 endef
 
-analysis: compile_mem
+analysis: compile
 	${QUARTUS_DIR}/bin/quartus_map --read_settings_files=on --write_settings_files=off ${QUARTUS_MACROS} ${PROJECT_NAME} -c ${PROJECT_NAME} --analysis_and_elaboration
 
 $(OUT_ASM): $(MEMDEP)
@@ -76,14 +76,15 @@ compile_all:
 gentable:
 	$(foreach x,$(CSVS),$(call execute-gentable,./$(x)))
 
-compile: $(VERILOG)
+simulate: $(VERILOG)
 	@echo ${MODELSIM_BIN} -c -do "vlog -sv -work work +incdir+$(abspath $(dir $<)) $(abspath $<)" -do exit
+
 .PHONY: compile
 
 testbench: compile
 	${MODELSIM_BIN} -c -do "vsim work.$(basename $(notdir $(VERILOG)))_tb" -do "run -all" -do exit
 
-compile_mem: $(MEMRES)
+compile: $(MEMRES)
 
 %.text_0.mem %.text_1.mem %.text_2.mem %.text_3.mem: %.asm
 	$(ASMC) -t mem -f $< -S $(words $(MEMSLICES)) .text

simulation/modelsim/UCL_project_y3_run_msim_rtl_verilog.do

@@ -5,15 +5,14 @@ if {[file exists rtl_work]} {
 vlib rtl_work
 vmap work rtl_work
 
-vlog -sv -work work +incdir+/home/min/devel/fpga/ucl_project_y3/src/blocks {/home/min/devel/fpga/ucl_project_y3/src/blocks/fifo.v}
 vlog -sv -work work +incdir+/home/min/devel/fpga/ucl_project_y3/src/blocks {/home/min/devel/fpga/ucl_project_y3/src/blocks/uart.v}
 vlog -sv -work work +incdir+/home/min/devel/fpga/ucl_project_y3/quartus {/home/min/devel/fpga/ucl_project_y3/quartus/pll_clk.v}
 vlog -sv -work work +incdir+/home/min/devel/fpga/ucl_project_y3/db {/home/min/devel/fpga/ucl_project_y3/db/pll_clk_altpll.v}
 vlog -sv -work work +incdir+/home/min/devel/fpga/ucl_project_y3/src/blocks {/home/min/devel/fpga/ucl_project_y3/src/blocks/rom.sv}
 vlog -sv -work work +incdir+/home/min/devel/fpga/ucl_project_y3/src {/home/min/devel/fpga/ucl_project_y3/src/project.sv}
-vlog -sv -work work +incdir+/home/min/devel/fpga/ucl_project_y3/src/blocks {/home/min/devel/fpga/ucl_project_y3/src/blocks/sdram_control.sv}
 vlog -sv -work work +incdir+/home/min/devel/fpga/ucl_project_y3/src/blocks {/home/min/devel/fpga/ucl_project_y3/src/blocks/reg_file.sv}
 vlog -sv -work work +incdir+/home/min/devel/fpga/ucl_project_y3/src/blocks {/home/min/devel/fpga/ucl_project_y3/src/blocks/alu.sv}
+vlog -sv -work work +incdir+/home/min/devel/fpga/ucl_project_y3/src/blocks {/home/min/devel/fpga/ucl_project_y3/src/blocks/ram.sv}
 vlog -sv -work work +incdir+/home/min/devel/fpga/ucl_project_y3/src {/home/min/devel/fpga/ucl_project_y3/src/top.sv}
 vlog -sv -work work +incdir+/home/min/devel/fpga/ucl_project_y3/src/risc {/home/min/devel/fpga/ucl_project_y3/src/risc/general.sv}
 vlog -sv -work work +incdir+/home/min/devel/fpga/ucl_project_y3/src/risc {/home/min/devel/fpga/ucl_project_y3/src/risc/datapath.sv}

src/project.sv

@@ -26,7 +26,7 @@ module com_block(
 	input  wire [7:0]	addr,
 	input  reg  [7:0]	in_data,
 	output reg  [7:0]	out_data,
-	output wire			interrupt,
+	output reg			interrupt,
 
 	// IO
 	output reg  [7:0]	leds,
@@ -71,18 +71,24 @@ module com_block(
 	//		reset_str[6] = 8'h10;
 	//end
 	
+	reg interrupt_reg;
+	assign interrupt = (key1 & interrupt_reg);
 	always_ff@(posedge clk) begin
 		if(rst) begin 
 			//reset_seq <= 0;
 			uart0_reg[2] <= 0;
+			//interrupt <= 0;
+			interrupt_reg <= 0;
 			leds <= 'b0000_0000;
 		end
 		//else if(~uart0_reg[2] && reset_seq != 7) reset_seq <= reset_seq + 1;
-		else begin 
+		else begin
 			case(addr)
 				8'h03: uart0_reg[2] <= in_data[2]; 
 				//8'h06: leds <= in_data;
 			endcase
+			if(~key1) interrupt_reg <= 1;
+			if(interrupt) interrupt_reg <= 0;
 			leds <= {5'b0, uart0_reg};
 		end
 	end

src/risc/controller.csv

@@ -1,56 +1,57 @@
-   instr, cdi.alu_op, cdi.selb, cdi.rw_en, cdi.selr, mem_rd, mem_wr, cdi.isize,cdi.selo ,cdi.stackop,cdi.pcop ,cdi.imoctl,cdi.aluf 
-    CPY0,   ALU_NONE,   SB_IMM,         1,   SR_IMM,      0,      0,         1,SO_MEML , ST_SKIP, PC_NONE ,IMO_NONE,2'b00 
-    CPY1,   ALU_NONE,   SB_IMM,         1,   SR_IMM,      0,      0,         1,SO_MEML , ST_SKIP, PC_NONE ,IMO_NONE,2'b00  
-    CPY2,   ALU_NONE,   SB_IMM,         1,   SR_IMM,      0,      0,         1,SO_MEML , ST_SKIP, PC_NONE ,IMO_NONE,2'b00  
-    CPY3,   ALU_NONE,   SB_IMM,         1,   SR_IMM,      0,      0,         1,SO_MEML , ST_SKIP, PC_NONE ,IMO_NONE,2'b00  
-    MOVE,   ALU_NONE,  SB_NONE,         1,   SR_REG,      0,      0,         0,SO_MEML , ST_SKIP, PC_NONE ,IMO_NONE,2'b00  
-     ADD,    ALU_ADD,   SB_REG,         1,  SR_ALUL,      0,      0,         0,SO_MEML , ST_SKIP, PC_NONE ,IMO_NONE,2'b00  
-     SUB,    ALU_SUB,   SB_REG,         1,  SR_ALUL,      0,      0,         0,SO_MEML , ST_SKIP, PC_NONE ,IMO_NONE,2'b00  
-     AND,    ALU_AND,   SB_REG,         1,  SR_ALUL,      0,      0,         0,SO_MEML , ST_SKIP, PC_NONE ,IMO_NONE,2'b00  
-      OR,     ALU_OR,   SB_REG,         1,  SR_ALUL,      0,      0,         0,SO_MEML , ST_SKIP, PC_NONE ,IMO_NONE,2'b00  
-     XOR,    ALU_XOR,   SB_REG,         1,  SR_ALUL,      0,      0,         0,SO_MEML , ST_SKIP, PC_NONE ,IMO_NONE,2'b00  
-    ADDI,    ALU_ADD,   SB_IMM,         1,  SR_ALUL,      0,      0,         1,SO_MEML , ST_SKIP, PC_NONE ,IMO_NONE,2'b00  
-    SUBI,    ALU_SUB,   SB_IMM,         1,  SR_ALUL,      0,      0,         1,SO_MEML , ST_SKIP, PC_NONE ,IMO_NONE,2'b00  
-    ANDI,    ALU_AND,   SB_IMM,         1,  SR_ALUL,      0,      0,         1,SO_MEML , ST_SKIP, PC_NONE ,IMO_NONE,2'b00  
-     ORI,     ALU_OR,   SB_IMM,         1,  SR_ALUL,      0,      0,         1,SO_MEML , ST_SKIP, PC_NONE ,IMO_NONE,2'b00  
-    XORI,    ALU_XOR,   SB_IMM,         1,  SR_ALUL,      0,      0,         1,SO_MEML , ST_SKIP, PC_NONE ,IMO_NONE,2'b00  
-     MUL,    ALU_MUL,   SB_REG,         1,  SR_ALUL,      0,      0,         0,SO_MEML , ST_SKIP, PC_NONE ,IMO_NONE,2'b00  
-     DIV,    ALU_DIV,   SB_REG,         1,  SR_ALUL,      0,      0,         0,SO_MEML , ST_SKIP, PC_NONE ,IMO_NONE,2'b00  
-     CI0,   ALU_NONE,  SB_NONE,         0,  SR_NONE,      0,      0,         0,SO_MEML , ST_SKIP, PC_NONE ,IMO_0,2'b00  
-     CI1,   ALU_NONE,  SB_NONE,         0,  SR_NONE,      0,      0,         0,SO_MEML , ST_SKIP, PC_NONE ,IMO_1,2'b00  
-     CI2,   ALU_NONE,  SB_NONE,         0,  SR_NONE,      0,      0,         0,SO_MEML , ST_SKIP, PC_NONE ,IMO_2,2'b00  
-    ADDC,    ALU_ADD,     SB_0,         1,  SR_ALUL,      0,      0,         0,SO_MEML , ST_SKIP, PC_NONE ,IMO_NONE,2'b01 
-    SUBC,    ALU_SUB,     SB_0,         1,  SR_ALUL,      0,      0,         0,SO_MEML , ST_SKIP, PC_NONE ,IMO_NONE,2'b01 
-     SLL,     ALU_SL,   SB_REG,         1,  SR_ALUL,      0,      0,         0,SO_MEML , ST_SKIP, PC_NONE ,IMO_NONE,2'b00  
-     SRL,     ALU_SR,   SB_REG,         1,  SR_ALUL,      0,      0,         0,SO_MEML , ST_SKIP, PC_NONE ,IMO_NONE,2'b00  
-     SRA,     ALU_RA,   SB_REG,         1,  SR_ALUL,      0,      0,         0,SO_MEML , ST_SKIP, PC_NONE ,IMO_NONE,2'b00  
-    LWHI,   ALU_NONE,  SB_NONE,         1,  SR_MEMH,      1,      0,         3,SO_MEML , ST_SKIP, PC_NONE ,IMO_NONE,2'b00  
-    SWHI,   ALU_NONE,  SB_NONE,         0,  SR_NONE,      0,      0,         0,SO_MEMH , ST_SKIP, PC_NONE ,IMO_NONE,2'b00  
-    LWLO,   ALU_NONE,  SB_NONE,         1,  SR_MEML,      1,      0,         3,SO_MEML , ST_SKIP, PC_NONE ,IMO_NONE,2'b00  
-    SWLO,   ALU_NONE,  SB_NONE,         0,  SR_NONE,      0,      1,         3,SO_MEML , ST_SKIP, PC_NONE ,IMO_NONE,2'b00  
-     INC,    ALU_ADD,     SB_1,         1,  SR_ALUL,      0,      0,         0,SO_MEML , ST_SKIP, PC_NONE ,IMO_NONE,2'b00  
-     DEC,    ALU_SUB,     SB_1,         1,  SR_ALUL,      0,      0,         0,SO_MEML , ST_SKIP, PC_NONE ,IMO_NONE,2'b00  
-   GETAH,   ALU_NONE,  SB_NONE,         1,  SR_ALUH,      0,      0,         0,SO_MEML , ST_SKIP, PC_NONE ,IMO_NONE,2'b00  
-   GETIF,   ALU_NONE,  SB_NONE,         1,  SR_INTR,      0,      0,         0,SO_MEML , ST_SKIP, PC_NONE ,IMO_NONE,2'b00  
-    PUSH,   ALU_NONE,  SB_NONE,         0,  SR_NONE,      0,      1,         0,SO_MEML ,  ST_SUB, PC_NONE ,IMO_NONE,2'b00  
-     POP,   ALU_NONE,  SB_NONE,         1,  SR_MEML,      1,      0,         0,SO_MEML ,  ST_ADD, PC_NONE ,IMO_NONE,2'b00  
-     COM,   ALU_NONE,  SB_NONE,         1,   SR_COM,      0,      0,         1, SO_COM , ST_SKIP, PC_NONE ,IMO_NONE,2'b00  
-     BEQ,   ALU_NONE,   SB_IMM,         0,  SR_NONE,      0,      0,(cdi.alu_comp[2:1] == 'b10)?1:3,SO_MEML , ST_SKIP,(cdi.alu_comp[2:1] == 'b10)?PC_IMM2:PC_NONE,IMO_NONE,2'b00  
-     BGT,   ALU_NONE,   SB_IMM,         0,  SR_NONE,      0,      0,(cdi.alu_comp[2:1] == 'b01)?1:3,SO_MEML , ST_SKIP,(cdi.alu_comp[2:1] == 'b01)?PC_IMM2:PC_NONE,IMO_NONE,2'b00  
-     BGE,   ALU_NONE,   SB_IMM,         0,  SR_NONE,      0,      0,(cdi.alu_comp[2]|cdi.alu_comp[1])?1:3,SO_MEML , ST_SKIP,(cdi.alu_comp[2]|cdi.alu_comp[1])?PC_IMM2:PC_NONE,IMO_NONE,2'b00  
-      BZ,     ALU_OR,     SB_0,         0,  SR_NONE,      0,      0,(cdi.alu_comp[0])?1:2,SO_MEML , ST_SKIP,(cdi.alu_comp[0])?PC_IMM:PC_NONE,IMO_NONE,2'b00  
-    CALL,   ALU_NONE,  SB_NONE,         0,  SR_NONE,      0,      1,         0,SO_MEML ,  ST_SUB,  PC_IMM ,IMO_NONE,2'b00  
-     RET,   ALU_NONE,  SB_NONE,         0,  SR_NONE,      1,      0,         2,SO_MEML ,  ST_ADD,  PC_MEM ,IMO_NONE,2'b00  
-    JUMP,   ALU_NONE,  SB_NONE,         0,  SR_NONE,      0,      0,         2,SO_MEML , ST_NONE,  PC_IMM,IMO_NONE,2'b00  
-    RETI,   ALU_NONE,  SB_NONE,         0,  SR_NONE,      1,      0,         2,SO_MEML ,  ST_SUB,  PC_MEM ,IMO_NONE,2'b00  
-     CLC,   ALU_NONE,  SB_NONE,         0,  SR_NONE,      0,      0,         0,SO_MEML , ST_SKIP, PC_NONE ,IMO_NONE,2'b00  
-    SETC,   ALU_NONE,  SB_NONE,         0,  SR_NONE,      0,      0,         0,SO_MEML , ST_SKIP, PC_NONE ,IMO_NONE,2'b00  
-     CLS,   ALU_NONE,  SB_NONE,         0,  SR_NONE,      0,      0,         0,SO_MEML , ST_SKIP, PC_NONE ,IMO_NONE,2'b00  
-    SETS,   ALU_NONE,  SB_NONE,         0,  SR_NONE,      0,      0,         0,SO_MEML , ST_SKIP, PC_NONE ,IMO_NONE,2'b00  
-   SSETS,   ALU_NONE,  SB_NONE,         0,  SR_NONE,      0,      0,         0,SO_MEML , ST_SKIP, PC_NONE ,IMO_NONE,2'b00  
-     CLN,   ALU_NONE,  SB_NONE,         0,  SR_NONE,      0,      0,         0,SO_MEML , ST_SKIP, PC_NONE ,IMO_NONE,2'b00  
-    SETN,   ALU_NONE,  SB_NONE,         0,  SR_NONE,      0,      0,         0,SO_MEML , ST_SKIP, PC_NONE ,IMO_NONE,2'b00  
-   SSETN,   ALU_NONE,  SB_NONE,         0,  SR_NONE,      0,      0,         0,SO_MEML , ST_SKIP, PC_NONE ,IMO_NONE,2'b00  
-   RJUMP,   ALU_NONE,  SB_NONE,         0,  SR_NONE,      0,      0,         2,SO_MEML , ST_SKIP, PC_NONE ,IMO_NONE,2'b00  
-    RBWI,   ALU_NONE,  SB_NONE,         0,  SR_NONE,      0,      0,         1,SO_MEML , ST_SKIP, PC_NONE ,IMO_NONE,2'b00  
- default,   ALU_NONE,  SB_NONE,         0,  SR_NONE,      0,      0,         0,SO_MEML , ST_SKIP, PC_NONE ,IMO_NONE,2'b00  
+   instr, cdi.alu_op, cdi.selb, cdi.rw_en, cdi.selr, mem_rd, mem_wr, cdi.isize,cdi.selo ,cdi.stackop,cdi.pcop ,cdi.imoctl,cdi.aluf ,cdi.intr_ctl
+    CPY0,   ALU_NONE,   SB_IMM,         1,   SR_IMM,      0,      0,         1,SO_MEML , ST_SKIP, PC_NONE ,IMO_NONE,2'b00 , INTR_NONE
+    CPY1,   ALU_NONE,   SB_IMM,         1,   SR_IMM,      0,      0,         1,SO_MEML , ST_SKIP, PC_NONE ,IMO_NONE,2'b00  , INTR_NONE
+    CPY2,   ALU_NONE,   SB_IMM,         1,   SR_IMM,      0,      0,         1,SO_MEML , ST_SKIP, PC_NONE ,IMO_NONE,2'b00  , INTR_NONE
+    CPY3,   ALU_NONE,   SB_IMM,         1,   SR_IMM,      0,      0,         1,SO_MEML , ST_SKIP, PC_NONE ,IMO_NONE,2'b00  , INTR_NONE
+    MOVE,   ALU_NONE,  SB_NONE,         1,   SR_REG,      0,      0,         0,SO_MEML , ST_SKIP, PC_NONE ,IMO_NONE,2'b00  , INTR_NONE
+     ADD,    ALU_ADD,   SB_REG,         1,  SR_ALUL,      0,      0,         0,SO_MEML , ST_SKIP, PC_NONE ,IMO_NONE,2'b00  , INTR_NONE
+     SUB,    ALU_SUB,   SB_REG,         1,  SR_ALUL,      0,      0,         0,SO_MEML , ST_SKIP, PC_NONE ,IMO_NONE,2'b00  , INTR_NONE
+     AND,    ALU_AND,   SB_REG,         1,  SR_ALUL,      0,      0,         0,SO_MEML , ST_SKIP, PC_NONE ,IMO_NONE,2'b00  , INTR_NONE
+      OR,     ALU_OR,   SB_REG,         1,  SR_ALUL,      0,      0,         0,SO_MEML , ST_SKIP, PC_NONE ,IMO_NONE,2'b00  , INTR_NONE
+     XOR,    ALU_XOR,   SB_REG,         1,  SR_ALUL,      0,      0,         0,SO_MEML , ST_SKIP, PC_NONE ,IMO_NONE,2'b00  , INTR_NONE
+    ADDI,    ALU_ADD,   SB_IMM,         1,  SR_ALUL,      0,      0,         1,SO_MEML , ST_SKIP, PC_NONE ,IMO_NONE,2'b00  , INTR_NONE
+    SUBI,    ALU_SUB,   SB_IMM,         1,  SR_ALUL,      0,      0,         1,SO_MEML , ST_SKIP, PC_NONE ,IMO_NONE,2'b00  , INTR_NONE
+    ANDI,    ALU_AND,   SB_IMM,         1,  SR_ALUL,      0,      0,         1,SO_MEML , ST_SKIP, PC_NONE ,IMO_NONE,2'b00  , INTR_NONE
+     ORI,     ALU_OR,   SB_IMM,         1,  SR_ALUL,      0,      0,         1,SO_MEML , ST_SKIP, PC_NONE ,IMO_NONE,2'b00  , INTR_NONE
+    XORI,    ALU_XOR,   SB_IMM,         1,  SR_ALUL,      0,      0,         1,SO_MEML , ST_SKIP, PC_NONE ,IMO_NONE,2'b00  , INTR_NONE
+     MUL,    ALU_MUL,   SB_REG,         1,  SR_ALUL,      0,      0,         0,SO_MEML , ST_SKIP, PC_NONE ,IMO_NONE,2'b00  , INTR_NONE
+     DIV,    ALU_DIV,   SB_REG,         1,  SR_ALUL,      0,      0,         0,SO_MEML , ST_SKIP, PC_NONE ,IMO_NONE,2'b00  , INTR_NONE
+     CI0,   ALU_NONE,  SB_NONE,         0,  SR_NONE,      0,      0,         0,SO_MEML , ST_SKIP, PC_NONE ,IMO_0,2'b00  , INTR_NONE
+     CI1,   ALU_NONE,  SB_NONE,         0,  SR_NONE,      0,      0,         0,SO_MEML , ST_SKIP, PC_NONE ,IMO_1,2'b00  , INTR_NONE
+     CI2,   ALU_NONE,  SB_NONE,         0,  SR_NONE,      0,      0,         0,SO_MEML , ST_SKIP, PC_NONE ,IMO_2,2'b00  , INTR_NONE
+    ADDC,    ALU_ADD,     SB_0,         1,  SR_ALUL,      0,      0,         0,SO_MEML , ST_SKIP, PC_NONE ,IMO_NONE,2'b01 , INTR_NONE
+    SUBC,    ALU_SUB,     SB_0,         1,  SR_ALUL,      0,      0,         0,SO_MEML , ST_SKIP, PC_NONE ,IMO_NONE,2'b01 , INTR_NONE
+     SLL,     ALU_SL,   SB_REG,         1,  SR_ALUL,      0,      0,         0,SO_MEML , ST_SKIP, PC_NONE ,IMO_NONE,2'b00  , INTR_NONE
+     SRL,     ALU_SR,   SB_REG,         1,  SR_ALUL,      0,      0,         0,SO_MEML , ST_SKIP, PC_NONE ,IMO_NONE,2'b00  , INTR_NONE
+     SRA,     ALU_RA,   SB_REG,         1,  SR_ALUL,      0,      0,         0,SO_MEML , ST_SKIP, PC_NONE ,IMO_NONE,2'b00  , INTR_NONE
+    LWHI,   ALU_NONE,  SB_NONE,         1,  SR_MEMH,      1,      0,         3,SO_MEML , ST_SKIP, PC_NONE ,IMO_NONE,2'b00  , INTR_NONE
+    SWHI,   ALU_NONE,  SB_NONE,         0,  SR_NONE,      0,      0,         0,SO_MEMH , ST_SKIP, PC_NONE ,IMO_NONE,2'b00  , INTR_NONE
+    LWLO,   ALU_NONE,  SB_NONE,         1,  SR_MEML,      1,      0,         3,SO_MEML , ST_SKIP, PC_NONE ,IMO_NONE,2'b00  , INTR_NONE
+    SWLO,   ALU_NONE,  SB_NONE,         0,  SR_NONE,      0,      1,         3,SO_MEML , ST_SKIP, PC_NONE ,IMO_NONE,2'b00  , INTR_NONE
+     INC,    ALU_ADD,     SB_1,         1,  SR_ALUL,      0,      0,         0,SO_MEML , ST_SKIP, PC_NONE ,IMO_NONE,2'b00  , INTR_NONE
+     DEC,    ALU_SUB,     SB_1,         1,  SR_ALUL,      0,      0,         0,SO_MEML , ST_SKIP, PC_NONE ,IMO_NONE,2'b00  , INTR_NONE
+   GETAH,   ALU_NONE,  SB_NONE,         1,  SR_ALUH,      0,      0,         0,SO_MEML , ST_SKIP, PC_NONE ,IMO_NONE,2'b00  , INTR_NONE
+   GETIF,   ALU_NONE,  SB_NONE,         1,  SR_INTR,      0,      0,         0,SO_MEML , ST_SKIP, PC_NONE ,IMO_NONE,2'b00  , INTR_NONE
+    PUSH,   ALU_NONE,  SB_NONE,         0,  SR_NONE,      0,      1,         0,SO_MEML ,  ST_SUB, PC_NONE ,IMO_NONE,2'b00  , INTR_NONE
+     POP,   ALU_NONE,  SB_NONE,         1,  SR_MEML,      1,      0,         0,SO_MEML ,  ST_ADD, PC_NONE ,IMO_NONE,2'b00  , INTR_NONE
+     COM,   ALU_NONE,  SB_NONE,         1,   SR_COM,      0,      0,         1, SO_COM , ST_SKIP, PC_NONE ,IMO_NONE,2'b00  , INTR_NONE
+     BEQ,   ALU_NONE,   SB_IMM,         0,  SR_NONE,      0,      0,(cdi.alu_comp[2:1] == 'b10)?1:3,SO_MEML , ST_SKIP,(cdi.alu_comp[2:1] == 'b10)?PC_IMM2:PC_NONE,IMO_NONE,2'b00  , INTR_NONE
+     BGT,   ALU_NONE,   SB_IMM,         0,  SR_NONE,      0,      0,(cdi.alu_comp[2:1] == 'b01)?1:3,SO_MEML , ST_SKIP,(cdi.alu_comp[2:1] == 'b01)?PC_IMM2:PC_NONE,IMO_NONE,2'b00  , INTR_NONE
+     BGE,   ALU_NONE,   SB_IMM,         0,  SR_NONE,      0,      0,(cdi.alu_comp[2]|cdi.alu_comp[1])?1:3,SO_MEML , ST_SKIP,(cdi.alu_comp[2]|cdi.alu_comp[1])?PC_IMM2:PC_NONE,IMO_NONE,2'b00  , INTR_NONE
+      BZ,     ALU_OR,     SB_0,         0,  SR_NONE,      0,      0,(cdi.alu_comp[0])?1:2,SO_MEML , ST_SKIP,(cdi.alu_comp[0])?PC_IMM:PC_NONE,IMO_NONE,2'b00  , INTR_NONE
+    CALL,   ALU_NONE,  SB_NONE,         0,  SR_NONE,      0,      1,         0,SO_MEML ,  ST_SUB,  PC_IMM ,IMO_NONE,2'b00  , INTR_NONE
+     RET,   ALU_NONE,  SB_NONE,         0,  SR_NONE,      1,      0,         2,SO_MEML ,  ST_ADD,  PC_MEM ,IMO_NONE,2'b00  , INTR_NONE
+    JUMP,   ALU_NONE,  SB_NONE,         0,  SR_NONE,      0,      0,         2,SO_MEML , ST_NONE,  PC_IMM ,IMO_NONE,2'b00  , INTR_NONE
+    RETI,   ALU_NONE,  SB_NONE,         0,  SR_NONE,      1,      0,         2,SO_MEML ,  ST_SUB,  PC_MEM ,IMO_NONE,2'b00  , INTR_RE
+     CLC,   ALU_NONE,  SB_NONE,         0,  SR_NONE,      0,      0,         0,SO_MEML , ST_SKIP, PC_NONE ,IMO_NONE,2'b00  , INTR_NONE
+    SETC,   ALU_NONE,  SB_NONE,         0,  SR_NONE,      0,      0,         0,SO_MEML , ST_SKIP, PC_NONE ,IMO_NONE,2'b00  , INTR_NONE
+     CLS,   ALU_NONE,  SB_NONE,         0,  SR_NONE,      0,      0,         0,SO_MEML , ST_SKIP, PC_NONE ,IMO_NONE,2'b00  , INTR_NONE
+    SETS,   ALU_NONE,  SB_NONE,         0,  SR_NONE,      0,      0,         0,SO_MEML , ST_SKIP, PC_NONE ,IMO_NONE,2'b00  , INTR_NONE
+   SSETS,   ALU_NONE,  SB_NONE,         0,  SR_NONE,      0,      0,         0,SO_MEML , ST_SKIP, PC_NONE ,IMO_NONE,2'b00  , INTR_NONE
+     CLN,   ALU_NONE,  SB_NONE,         0,  SR_NONE,      0,      0,         0,SO_MEML , ST_SKIP, PC_NONE ,IMO_NONE,2'b00  , INTR_NONE
+    SETN,   ALU_NONE,  SB_NONE,         0,  SR_NONE,      0,      0,         0,SO_MEML , ST_SKIP, PC_NONE ,IMO_NONE,2'b00  , INTR_NONE
+   SSETN,   ALU_NONE,  SB_NONE,         0,  SR_NONE,      0,      0,         0,SO_MEML , ST_SKIP, PC_NONE ,IMO_NONE,2'b00  , INTR_NONE
+   RJUMP,   ALU_NONE,  SB_NONE,         0,  SR_NONE,      0,      0,         2,SO_MEML , ST_SKIP, PC_NONE ,IMO_NONE,2'b00  , INTR_NONE
+    RBWI,   ALU_NONE,  SB_NONE,         0,  SR_NONE,      0,      0,         1,SO_MEML , ST_SKIP, PC_NONE ,IMO_NONE,2'b00  , INTR_NONE
+   INTRE,   ALU_NONE,  SB_NONE,         0,  SR_NONE,      0,      0,         2,SO_MEML , ST_SKIP, PC_NONE ,IMO_NONE,2'b00  , INTR_WE
+ default,   ALU_NONE,  SB_NONE,         0,  SR_NONE,      0,      0,         0,SO_MEML , ST_SKIP, PC_NONE ,IMO_NONE,2'b00  , INTR_NONE

src/risc/cpu.sv

@@ -39,7 +39,8 @@ module risc8_cpu(processor_port port);
 			.com_addr(port.com_addr),
 			.com_rd(port.com_rd),
 			.com_wr(port.com_wr),
-			.pc(pc)
+			.pc(pc),
+			.interrupt(port.com_interrupt)
 	);
 
 endmodule

src/risc/datapath.sv

@@ -18,9 +18,9 @@ module datapath8(
 	
 	// immidate overrride
 	word imo0, imo1, imo2;
-	reg imo0_en, imo1_en, imo2_en, imo_en;
-	
+	reg imo0_en, imo1_en, imo2_en, imo_en;	
 	reg [23:0] imm;
+
 	always_comb begin
 		imm[7:0] = (imo_en & imo2_en) ? imo2 : immr[7:0];
 		imm[15:8] = (imo_en & imo1_en) ? imo1 : immr[15:8];
@@ -87,55 +87,74 @@ module datapath8(
 	);
 
 	// ======================== //
-	// 		Program Counter 	//
+	// 		  Interrupt	 		//
 	// ======================== //
 
-	logic bconst, pc_halted, pchf; // Use immediate to branch
-	word pc_off; // Program counter offset
-	reg [15:0] pcn, pca, pcx, pch, pcp, pcn0; // Program Counter Previous, to add
-	assign pchf = (cdi.pcop == PC_MEM) & ~pc_halted;
+	word interrupt_flag, intre, intrr;
 	always_ff@(posedge clk) begin
-			if(rst) begin 
-				pcx <= 0;
-				pc_halted <= 0;
-			end else begin
-				pcx <= pcn;
-				pch <= pcn;
-				if (pchf) pc_halted <= 1;
-				else pc_halted <= 0;
+		if(rst) begin
+			interrupt_flag <= 0;
+			intre <= 0;
+			intrr <= 0;
+		end
+		else begin 
+			if(interrupt) begin
+				interrupt_flag <= com_rd;
+				intrr <= pc;
 			end
+			if(cdi.intr_ctl == INTR_WE) intre <= imm[7:0];
+		end
 	end
-	assign pcp = (pchf) ? pch : pcn;
-	assign pc = (rst) ? 0 : pcp;
 	
-	always_comb begin
-		bconst = 0;  // FIXME: temporary
+	
+	// ======================== //
+	// 		Program Counter 	//
+	// ======================== //
+
+	logic pc_halted, intr_re, pcs, pchf; // Use immediate to branch
+	word pc_off; // Program counter offset
+	reg [15:0] pcn, pch, pca, pcb, pcn0; // Program Counter Previous, to add
+	assign pchf = (cdi.pcop == PC_MEM) & ~pc_halted;
+	always_comb begin 
 		pc_off = { 
 			5'b0000_0, 
 			cdi.isize[0]&cdi.isize[1], 
 			cdi.isize[0]^cdi.isize[1], 
 			(~cdi.isize[1]&~cdi.isize[0])|(cdi.isize[1]&~cdi.isize[0])
 		}; // Adding 1 to 2bit value.
+
+		intr_re = cdi.intr_ctl == INTR_RE;
+		pcs = intr_re | interrupt | rst;
+		
 		case(cdi.pcop)
-			PC_NONE: pcn0 = pcx;
+			PC_NONE: pcn0 = pcb;
 			PC_MEM : pcn0 = mem_rd;
 			PC_IMM : pcn0 = {imm[7:0], imm[15:8]};
 			PC_IMM2: pcn0 = {imm[15:8], imm[23:16]};
-			default: pcn0 = pcx;
+			default: pcn0 = pcb;
 		endcase
+
 		pcn = (cdi.pcop == PC_IMM | cdi.pcop == PC_IMM2) ? pcn0 : pcn0 + pc_off;
-		//pca = (bconst) ? {imm[7:0], imm[15:8]} : pc;
-		//pcn = pca + pc_off;
+		pca = (pchf) ? pch : pcn;
+		casez({intr_re, interrupt, rst})
+			3'b000: pcb = pch;
+			3'b100: pcb = intrr;
+			3'b?10: pcb = intre;
+			3'b??1: pcb = 16'h0000;
+		endcase
+		pc = (pcs) ? pcb : pca;
+		
+
 	end
 	
-	// ======================== //
-	// 		  Interrupt	 		//
-	// ======================== //
-
-	word interrupt_flag;
 	always_ff@(posedge clk) begin
-		if(rst) interrupt_flag <= 0;
-		else if(interrupt) interrupt_flag <= com_rd;
+			if(rst) begin 
+				pch <= 0;
+				pc_halted <= 0;
+			end else begin
+				pch <= pcn;
+				pc_halted <= pchf;
+			end
 	end
 	
 	
@@ -149,9 +168,9 @@ module datapath8(
 	always_comb begin
 		sp_add = (cdi.stackop == ST_ADD) ? 'h0001 : 'hffff;
 		sp_next = sp + sp_add;
-		sp_addr = {9'b1111_1111_1, (cdi.stackop == ST_ADD) ? sp_next[15:0] : sp[15:0]};
+		sp_addr = {8'b1111_1111, (cdi.stackop == ST_ADD) ? sp_next[15:0] : sp[15:0]};
 		st_rd = {mem_rd[7:0]};
-		st_wr = (cdi.pcop == PC_IMM) ? pcx : {8'h00, r1};
+		st_wr = (cdi.pcop == PC_IMM) ? pch : {8'h00, r1};
 		//if(sp[0]) begin
 			//st_wr = {'h00, r1};
 			//st_rd = {mem_rd[7:0]};

src/risc/general.sv

@@ -74,7 +74,7 @@ package risc8_pkg;
         SSETN=8'b1111_1011,  // i15-11
         RJUMP=8'b1111_1100,  // i15-12
         RBWI =8'b1111_1101,  // i15-13 Replace ALU src B with immediate
-        i254 =8'b1111_1110,  // i15-14
+        INTRE=8'b1111_1110,  // i15-14 Interrupt entry
         i255 =8'b1111_1111   // i15-15
 		
 	} e_instr;               
@@ -138,6 +138,11 @@ package risc8_pkg;
 		IMO_2 	 = 2'b11
 	} e_imo_ctl;
 
+	typedef enum logic [1:0] {
+		INTR_NONE = 2'b0?,
+		INTR_WE   = 2'b10,
+		INTR_RE	  = 2'b11
+	} e_intr_ctl;
 
 endpackage
 
@@ -152,6 +157,7 @@ interface risc8_cdi;  // Control Datapath interface
 	e_selo selo;
 	e_stackop stackop;
 	e_pcop pcop;
+	e_intr_ctl intr_ctl;
 	logic [2:0] alu_comp;
 	logic [1:0] aluf;
 	
@@ -165,13 +171,15 @@ interface risc8_cdi;  // Control Datapath interface
 	modport datapath(
 		input alu_op, selb, sign, alu_not, selo, stackop, pcop,
 		output alu_comp,
-		input a1, a2, a3, rw_en, selr, mem_h, isize, pc_halt, imoctl, aluf
+		input a1, a2, a3, rw_en, selr, mem_h, isize, pc_halt, imoctl, aluf,
+		intr_ctl
 	);
 	
 	modport control(
 		output alu_op, selb, sign, alu_not, selo, stackop, pcop,
 		input alu_comp,
-		output a1, a2, a3, rw_en, selr, mem_h, isize, pc_halt, imoctl, aluf
+		output a1, a2, a3, rw_en, selr, mem_h, isize, pc_halt, imoctl, aluf,
+		intr_ctl
 	);
 
 endinterface

src/top.sv

@@ -41,7 +41,7 @@ module top(
 	wire fclk; // Fast clock 		100MHz 		(for sdram)
 	wire aclk; // Auxiliary clock 	32,768kHz 	(for timers)
 	
-	pll_clkpll_clk0 (
+	pll_clk pll_clk0 (
 			.inclk0(CLK50),
 			.areset(0),
 			.c0(fclk),
@@ -103,7 +103,7 @@ module top(
 		.switches(SWITCH),
 		.uart0_rx(RX),
 		.uart0_tx(TX),
-		.key1(~KEY[1])
+		.key1(KEY[1])
 	);
 
 	// Processor
@@ -194,6 +194,10 @@ module top_tb;
 
 			#1100ns;
 			KEY[0] = 1;
+			#20us;
+			KEY[1] = 0;
+			#5us;
+			KEY[1] = 1;
 			#300us;
 			$stop;
 	end

tools/risc8asm.py

@@ -3,7 +3,7 @@ import sys
 import math
 from os import path, mkdir
 
-import nasm_compiler as compiler
+import asm_compiler as compiler
 
 asmc = compiler.Compiler(byte_order='big')
 asmc.add_reg('r0', 0)
@@ -59,6 +59,7 @@ asmc.add_instr(compiler.Instruction('BZ   ', '1101_??11', 2))
 asmc.add_instr(compiler.Instruction('CALL ', '1111_0000', 2))
 asmc.add_instr(compiler.Instruction('RET  ', '1111_0001'))
 asmc.add_instr(compiler.Instruction('JUMP ', '1111_0010', 2))
+asmc.add_instr(compiler.Instruction('INTRE', '1111_1110', 2))
 asmc.add_instr(compiler.Instruction('RETI ', '1111_0011'))
 asmc.add_instr(compiler.Instruction('CLC  ', '1111_0100'))
 asmc.add_instr(compiler.Instruction('SETC ', '1111_0101'))