Do not simulate rst signal

simulation/modelsim/UCL_project_y3_run_msim_rtl_verilog.do

@@ -13,17 +13,13 @@ vlog -sv -work work +incdir+/home/min/devel/fpga/ucl_project_y3/src {/home/min/d
 vlog -sv -work work +incdir+/home/min/devel/fpga/ucl_project_y3/src/blocks {/home/min/devel/fpga/ucl_project_y3/src/blocks/reg_file.sv}
 vlog -sv -work work +incdir+/home/min/devel/fpga/ucl_project_y3/src/blocks {/home/min/devel/fpga/ucl_project_y3/src/blocks/alu.sv}
 vlog -sv -work work +incdir+/home/min/devel/fpga/ucl_project_y3/src/blocks {/home/min/devel/fpga/ucl_project_y3/src/blocks/ram.sv}
-vlog -sv -work work +incdir+/home/min/devel/fpga/ucl_project_y3/src {/home/min/devel/fpga/ucl_project_y3/src/top.sv}
-vlog -sv -work work +incdir+/home/min/devel/fpga/ucl_project_y3/src/risc {/home/min/devel/fpga/ucl_project_y3/src/risc/general.sv}
-vlog -sv -work work +incdir+/home/min/devel/fpga/ucl_project_y3/src/risc {/home/min/devel/fpga/ucl_project_y3/src/risc/datapath.sv}
-vlog -sv -work work +incdir+/home/min/devel/fpga/ucl_project_y3/src/risc {/home/min/devel/fpga/ucl_project_y3/src/risc/cpu.sv}
-vlog -sv -work work +incdir+/home/min/devel/fpga/ucl_project_y3/src/risc {/home/min/devel/fpga/ucl_project_y3/src/risc/controller.sv}
-
+vlog -sv -work work +incdir+/home/min/devel/fpga/ucl_project_y3/src/blocks {/home/min/devel/fpga/ucl_project_y3/src/blocks/adder.sv}
+vlog -sv -work work +incdir+/home/min/devel/fpga/ucl_project_y3/src/blocks {/home/min/devel/fpga/ucl_project_y3/src/blocks/debug.sv}
 vlog -sv -work work +incdir+/home/min/devel/fpga/ucl_project_y3/src {/home/min/devel/fpga/ucl_project_y3/src/top.sv}
 
 vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -voptargs="+acc"  top_tb
 
-add wave *
-view structure
-view signals
-run -all
+#add wave *
+#view structure
+#view signals
+#run -all

src/top.sv

@@ -39,13 +39,14 @@ module top(
 	
 	`ifdef SYNTHESIS
 		initial $display("Assuming this is synthesis");
+		wire debug_rst;
+		sys_ss#("RST") sys_ss_rst(debug_rst);
+		assign rst = ~KEY[0] | debug_rst;
 	`else
 		initial $display("Assuming this is simulation");
+		assign rst = ~KEY[0];
 	`endif
 	
-	wire debug_rst;
-	sys_ss#("RST") sys_ss_rst(debug_rst);
-	assign rst = ~KEY[0] | debug_rst;
 	
 	/* Clocks */
 	wire mclk; // Master clock 		1MHz 		(for cpu)