Added debugging probes to OISC

Added a bunch of debugging probes/sources that can be synthesised with
DEBUG enviroment variable

src/blocks/debug.sv

@@ -55,15 +55,39 @@ module altsource_probe_top
     
 endmodule
 
-module sys_ss (output wire source);
+
+module sys_comb(source, probe);
 	parameter NAME = "";
+	parameter WIDTH = 1;
+	input wire[WIDTH-1:0] probe;
+	output wire[WIDTH-1:0] source;
+
+	altsource_probe_top #(
+		.sld_auto_instance_index ("YES"),
+		.sld_instance_index      (0),
+		.instance_id             (NAME),
+		.probe_width             (WIDTH),
+		.source_width            (WIDTH),
+		.enable_metastability    ("NO")
+	) in_system_sources_probes_0 (
+		.probe (probe),       // probes.probe
+		.source(source),      // sources.source
+		.source_ena ('d0)    // (terminated)
+	);
+endmodule
+
+
+module sys_ss (source);
+	parameter NAME = "";
+	parameter WIDTH = 1;
+	output wire[WIDTH-1:0] source;
 
 	altsource_probe_top #(
 		.sld_auto_instance_index ("YES"),
 		.sld_instance_index      (0),
 		.instance_id             (NAME),
 		.probe_width             (0),
-		.source_width            (1),
+		.source_width            (WIDTH),
 		.source_initial_value    ("0"),
 		.enable_metastability    ("NO")
 	) in_system_sources_probes_0 (

src/const.sv

@@ -4,3 +4,5 @@
 // Number of 16bit cells in ram 
 `define RAM_SIZE 4096  
 
+// Add debugging hardware to processor
+`define DEBUG

src/oisc/cpu.sv

@@ -21,8 +21,15 @@ module oisc8_cpu(processor_port port);
 	//);
 	//Port #(.ADDR)
 	//PortOutput p_null(.bus(bus0.port),.data_to_bus(`DWIDTH'd0));
-	PortReg#(.ADDR_SRC(REG0R), .ADDR_DST(REG0)) p_reg0(.bus(bus0.port));
-	PortReg#(.ADDR_SRC(REG1R), .ADDR_DST(REG1)) p_reg1(.bus(bus0.port));
+	reg [`DWIDTH-1:0] reg0, reg1;
+	PortReg#(.ADDR_SRC(REG0R), .ADDR_DST(REG0)) p_reg0(.bus(bus0.port),.register(reg0));
+	PortReg#(.ADDR_SRC(REG1R), .ADDR_DST(REG1)) p_reg1(.bus(bus0.port),.register(reg1));
+	
+	`ifdef DEBUG
+	sys_sp#("REG0", `DWIDTH) sys_reg0(reg0);
+	sys_sp#("REG1", `DWIDTH) sys_reg1(reg1);
+	`endif
+
 	pc_block#(.PROGRAM("../../memory/oisc8.text")) pc0(bus0.port, bus0.iport);
 	alu_block alu0(bus0.port);
 	mem_block ram0(bus0.port, port);
@@ -49,6 +56,12 @@ module oisc_com_block(IBus.port bus, processor_port port);
 	PortOutput#(.ADDR(COMDR)) p_comdr(
 			.bus(bus),.data_to_bus(port.com_rd),.rd(rd)
 	);
+	
+	`ifdef DEBUG
+	sys_sp#("COMA", 8) sys_coma(addr);
+	sys_sp#("COMW", 8) sys_comw(port.com_wr);
+	sys_sp#("COMR", 8) sys_comd(port.com_rd);
+	`endif
 endmodule
 
 module mem_block(IBus.port bus, processor_port port);
@@ -185,6 +198,11 @@ module alu_block(IBus.port bus);
 	PortNReg#(ALUACC0, ALUACC0R) p_aluacc0(.bus(bus),.register(acc0));
 	PortNReg#(ALUACC1, ALUACC1R) p_aluacc1(.bus(bus),.register(acc1));
 
+	`ifdef DEBUG
+	sys_sp#("ALU0", `DWIDTH) sys_alu0(acc0);
+	sys_sp#("ALU1", `DWIDTH) sys_alu1(acc1);
+	`endif
+
 	//carry_lookahead_adder#(.WIDTH(`DWIDTH)) alu_adder0(acc0,acc1,reg_add);
 	wire [`DWIDTH-1:0] reg_add;
 	wire reg_addc, add_rd;

src/oisc/romblock.sv

@@ -24,8 +24,7 @@ module pc_block(IBus.port bus, IBus.iport port);
 	reg[15:0] pc, pcr; // Program counter
 	reg[15:0] pointer;  // Instruction pointer accumulator
 	reg[7:0] comp_acc;  // Compare accumulator
-	reg comp_zero;
-	reg rst0, pc0; // delayed reset and lsb of pc
+	reg comp_zero, pc0;
 
 	/* ====================
 	*       ROM BLOCK
@@ -51,9 +50,13 @@ module pc_block(IBus.port bus, IBus.iport port);
 	assign instrB = instrBlock[13:1];
 	assign instr = pc0 ? instrA : instrB;
 
-	`ifndef SYNTHESIS
+	`ifdef DEBUG
 	reg [15:0] pcp;  // Current program counter for debugging
 	always_ff@(posedge bus.clk) pcp <= pc;
+	sys_sp#("PC", 16) sys_pc(pcp);
+	sys_sp#("INST", 13) sys_instr(instr);
+	sys_sp#("BRPT", 16) sys_brpt(pointer);
+	sys_sp#("DATA", 16) sys_data(port.data);
 	`endif
 	
 
@@ -61,7 +64,6 @@ module pc_block(IBus.port bus, IBus.iport port);
 	//assign pcn = comp_zero|bus.rst ? pointer : pc + 1;
 	assign pcn = pc + 1;
 	always_ff@(posedge bus.clk) begin
-		rst0 <= bus.rst;
 		if(bus.rst) begin 
 			pcr <= 16'd0;
 			pc0 <= 1'b0;
@@ -70,7 +72,7 @@ module pc_block(IBus.port bus, IBus.iport port);
 			pc0 <= pc[0];
 		end
 	end
-	always_comb casez({comp_zero,bus.rst|rst0})
+	always_comb casez({comp_zero,bus.rst})
 		2'b00: pc = pcr;
 		2'b10: pc = pointer;
 		2'b?1: pc = 16'd0;

src/top.sv

@@ -54,6 +54,20 @@ module top(
 	wire fclk; // Fast clock 		100MHz 		(for sdram)
 	wire aclk; // Auxiliary clock 	32,768kHz 	(for timers)
 
+	`ifdef DEBUG
+	wire mclk1, mclk0, clkd;
+	sys_ss#("CLKD", 1) sys_clkd(clkd);
+	sys_ss#("MCLK", 1) sys_mclk(mclk0);
+	assign mclk = clkd ? mclk0 : mclk1;
+
+	pll_clk pll_clk0 (
+			.inclk0(CLK50),
+			.areset(0),
+			.c0(fclk),
+			.c1(mclk1),
+			.c2(aclk)
+	);
+	`else
 	pll_clk pll_clk0 (
 			.inclk0(CLK50),
 			.areset(0),
@@ -61,6 +75,7 @@ module top(
 			.c1(mclk),
 			.c2(aclk)
 	);
+	`endif
 
 	//clk_dive#(28'd50) clk_div_mclk(CLK50, mclk);
 	//assign mclk = ~KEY[1];	
@@ -82,7 +97,7 @@ module top(
 	`endif
 	ram_block0(ram_addr[11:0], mclk, ram_wr_data, ram_wr_en, ram_rd_en, ram_rd_data);
 	
-	`ifdef SYNTHESIS
+	`ifdef DEBUG
 		reg[23:0] ram_addr_rd_pr, ram_addr_wr_pr;
 		reg[15:0] ram_data_rd_pr, ram_data_wr_pr;
 		reg ram_rd_pr0;
@@ -127,7 +142,11 @@ module top(
 	wire com0_interrupt;
 
 	com_block com0 (
+		`ifdef DEBUG
+		.clk(mclk1),
+		`else
 		.clk(mclk),
+		`endif
 		.rst(rst),
 		.addr(com0_addr),
 		.in_data(com0_wr),